/* * Generated by gen_defines.py * * DTS input file: * /home/mike/Documents/ncs/v2.7.0/conexio-firmware-sdk/samples/conexio_stratus/mqtt_control/builddk/mcuboot/zephyr/zephyr.dts.pre * * Directories with bindings: * /home/mike/Documents/ncs/v2.7.0/nrf/dts/bindings, $ZEPHYR_BASE/boards/nordic/nrf9161dk/dts/bindings, $ZEPHYR_BASE/dts/bindings * * Node dependency ordering (ordinal and path): * 0 / * 1 /aliases * 2 /analog-connector * 3 /chosen * 4 /connector * 5 /entropy_bt_hci * 6 /soc * 7 /soc/interrupt-controller@e000e100 * 8 /soc/gpiote@5000d000 * 9 /soc/peripheral@50000000 * 10 /soc/peripheral@50000000/gpio@842500 * 11 /gpio-reset * 12 /soc/peripheral@50000000/timer@10000 * 13 /sw-pwm * 14 /buttons * 15 /buttons/button_0 * 16 /buttons/button_1 * 17 /buttons/button_2 * 18 /buttons/button_3 * 19 /cpus * 20 /cpus/cpu@0 * 21 /cpus/cpu@0/mpu@e000ed90 * 22 /leds * 23 /leds/led_0 * 24 /leds/led_1 * 25 /leds/led_2 * 26 /leds/led_3 * 27 /pin-controller * 28 /pin-controller/i2c2_default * 29 /pin-controller/i2c2_default/group1 * 30 /pin-controller/i2c2_sleep * 31 /pin-controller/i2c2_sleep/group1 * 32 /pin-controller/pwm0_default * 33 /pin-controller/pwm0_default/group1 * 34 /pin-controller/pwm0_sleep * 35 /pin-controller/pwm0_sleep/group1 * 36 /pin-controller/spi3_default * 37 /pin-controller/spi3_default/group1 * 38 /pin-controller/spi3_sleep * 39 /pin-controller/spi3_sleep/group1 * 40 /pin-controller/uart0_default * 41 /pin-controller/uart0_default/group1 * 42 /pin-controller/uart0_default/group2 * 43 /pin-controller/uart0_sleep * 44 /pin-controller/uart0_sleep/group1 * 45 /pin-controller/uart1_default * 46 /pin-controller/uart1_default/group1 * 47 /pin-controller/uart1_default/group2 * 48 /pin-controller/uart1_sleep * 49 /pin-controller/uart1_sleep/group1 * 50 /soc/peripheral@50000000/pwm@21000 * 51 /pwmleds * 52 /pwmleds/pwm_led_0 * 53 /reserved-memory * 54 /reserved-memory/image_modem@20016000 * 55 /reserved-memory/image_ns@20020000 * 56 /reserved-memory/image_s@20000000 * 57 /soc/crypto@50840000 * 58 /soc/ctrlap@50006000 * 59 /soc/ficr@ff0000 * 60 /soc/gpiote@40031000 * 61 /soc/memory@20000000 * 62 /soc/spu@50003000 * 63 /soc/timer@e000e010 * 64 /soc/uicr@ff8000 * 65 /soc/peripheral@50000000/adc@e000 * 66 /soc/peripheral@50000000/clock@5000 * 67 /soc/peripheral@50000000/dppic@17000 * 68 /soc/peripheral@50000000/egu@1b000 * 69 /soc/peripheral@50000000/egu@1c000 * 70 /soc/peripheral@50000000/egu@1d000 * 71 /soc/peripheral@50000000/egu@1e000 * 72 /soc/peripheral@50000000/egu@1f000 * 73 /soc/peripheral@50000000/egu@20000 * 74 /soc/peripheral@50000000/i2c@8000 * 75 /soc/peripheral@50000000/i2c@9000 * 76 /soc/peripheral@50000000/i2c@b000 * 77 /soc/peripheral@50000000/i2s@28000 * 78 /soc/peripheral@50000000/ipc@2a000 * 79 /soc/peripheral@50000000/kmu@39000 * 80 /soc/peripheral@50000000/pdm@26000 * 81 /soc/peripheral@50000000/pwm@22000 * 82 /soc/peripheral@50000000/pwm@23000 * 83 /soc/peripheral@50000000/pwm@24000 * 84 /soc/peripheral@50000000/regulator@4000 * 85 /soc/peripheral@50000000/rtc@14000 * 86 /soc/peripheral@50000000/rtc@15000 * 87 /soc/peripheral@50000000/spi@8000 * 88 /soc/peripheral@50000000/spi@9000 * 89 /soc/peripheral@50000000/spi@a000 * 90 /soc/peripheral@50000000/timer@f000 * 91 /soc/peripheral@50000000/timer@11000 * 92 /soc/peripheral@50000000/uart@8000 * 93 /soc/peripheral@50000000/uart@9000 * 94 /soc/peripheral@50000000/uart@a000 * 95 /soc/peripheral@50000000/uart@b000 * 96 /soc/peripheral@50000000/vmc@3a000 * 97 /soc/peripheral@50000000/watchdog@18000 * 98 /soc/peripheral@50000000/flash-controller@39000 * 99 /soc/peripheral@50000000/flash-controller@39000/flash@0 * 100 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions * 101 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0 * 102 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000 * 103 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000 * 104 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@85000 * 105 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c5000 * 106 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@fa000 * 107 /soc/peripheral@50000000/i2c@a000 * 108 /soc/peripheral@50000000/i2c@a000/pcal6408a@21 * 109 /soc/peripheral@50000000/power@5000 * 110 /soc/peripheral@50000000/power@5000/gpregret1@51c * 111 /soc/peripheral@50000000/power@5000/gpregret2@520 * 112 /soc/peripheral@50000000/spi@b000 * 113 /soc/peripheral@50000000/spi@b000/gd25wb256e3ir@1 * * Definitions derived from these nodes in dependency order are next, * followed by /chosen nodes. */ /* Used to remove brackets from around a single argument */ #define DT_DEBRACKET_INTERNAL(...) __VA_ARGS__ /* * Devicetree node: / * * Node identifier: DT_N */ /* Node's full path: */ #define DT_N_PATH "/" /* Node's name with unit-address: */ #define DT_N_FULL_NAME "/" /* Helper macros for child nodes of this node. */ #define DT_N_CHILD_NUM 14 #define DT_N_CHILD_NUM_STATUS_OKAY 12 #define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_sw_pwm) fn(DT_N_S_cpus) fn(DT_N_S_leds) fn(DT_N_S_pwmleds) fn(DT_N_S_buttons) fn(DT_N_S_gpio_reset) fn(DT_N_S_connector) fn(DT_N_S_analog_connector) fn(DT_N_S_reserved_memory) #define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sw_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_reset) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory) #define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_sw_pwm, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_gpio_reset, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_analog_connector, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) #define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sw_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_reset, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory, __VA_ARGS__) #define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_leds) fn(DT_N_S_pwmleds) fn(DT_N_S_buttons) fn(DT_N_S_connector) fn(DT_N_S_analog_connector) fn(DT_N_S_reserved_memory) #define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory) #define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_analog_connector, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) #define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_ORD 0 #define DT_N_ORD_STR_SORTABLE 00000 /* Ordinals for what this node depends on directly: */ #define DT_N_REQUIRES_ORDS /* nothing */ /* Ordinals for what depends directly on this node: */ #define DT_N_SUPPORTS_ORDS \ 1, /* /aliases */ \ 2, /* /analog-connector */ \ 3, /* /chosen */ \ 4, /* /connector */ \ 5, /* /entropy_bt_hci */ \ 6, /* /soc */ \ 11, /* /gpio-reset */ \ 13, /* /sw-pwm */ \ 14, /* /buttons */ \ 19, /* /cpus */ \ 22, /* /leds */ \ 27, /* /pin-controller */ \ 51, /* /pwmleds */ \ 53, /* /reserved-memory */ /* Existence and alternate IDs: */ #define DT_N_EXISTS 1 #define DT_N_INST_0_nordic_nrf9161_dk_nrf9161 DT_N /* Macros for properties that are special in the specification: */ #define DT_N_REG_NUM 0 #define DT_N_RANGES_NUM 0 #define DT_N_FOREACH_RANGE(fn) #define DT_N_IRQ_NUM 0 #define DT_N_IRQ_LEVEL 0 #define DT_N_COMPAT_MATCHES_nordic_nrf9161_dk_nrf9161 1 #define DT_N_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_COMPAT_MODEL_IDX_0 "nrf9161-dk-nrf9161" #define DT_N_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_P_compatible {"nordic,nrf9161-dk-nrf9161"} #define DT_N_P_compatible_IDX_0 "nordic,nrf9161-dk-nrf9161" #define DT_N_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf9161-dk-nrf9161 #define DT_N_P_compatible_IDX_0_STRING_TOKEN nordic_nrf9161_dk_nrf9161 #define DT_N_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF9161_DK_NRF9161 #define DT_N_P_compatible_IDX_0_EXISTS 1 #define DT_N_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N, compatible, 0) #define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N, compatible, 0) #define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N, compatible, 0, __VA_ARGS__) #define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N, compatible, 0, __VA_ARGS__) #define DT_N_P_compatible_LEN 1 #define DT_N_P_compatible_EXISTS 1 /* * Devicetree node: /aliases * * Node identifier: DT_N_S_aliases */ /* Node's full path: */ #define DT_N_S_aliases_PATH "/aliases" /* Node's name with unit-address: */ #define DT_N_S_aliases_FULL_NAME "aliases" /* Node parent (/) identifier: */ #define DT_N_S_aliases_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_aliases_CHILD_IDX 1 /* Helper macros for child nodes of this node. */ #define DT_N_S_aliases_CHILD_NUM 0 #define DT_N_S_aliases_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_aliases_FOREACH_CHILD(fn) #define DT_N_S_aliases_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_aliases_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_aliases_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_aliases_ORD 1 #define DT_N_S_aliases_ORD_STR_SORTABLE 00001 /* Ordinals for what this node depends on directly: */ #define DT_N_S_aliases_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_aliases_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_aliases_REG_NUM 0 #define DT_N_S_aliases_RANGES_NUM 0 #define DT_N_S_aliases_FOREACH_RANGE(fn) #define DT_N_S_aliases_IRQ_NUM 0 #define DT_N_S_aliases_IRQ_LEVEL 0 #define DT_N_S_aliases_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_aliases_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /analog-connector * * Node identifier: DT_N_S_analog_connector * * Binding (compatible = arduino,uno-adc): * $ZEPHYR_BASE/dts/bindings/adc/arduino,uno-adc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_analog_connector_PATH "/analog-connector" /* Node's name with unit-address: */ #define DT_N_S_analog_connector_FULL_NAME "analog-connector" /* Node parent (/) identifier: */ #define DT_N_S_analog_connector_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_analog_connector_CHILD_IDX 12 /* Helper macros for child nodes of this node. */ #define DT_N_S_analog_connector_CHILD_NUM 0 #define DT_N_S_analog_connector_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_analog_connector_FOREACH_CHILD(fn) #define DT_N_S_analog_connector_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_analog_connector_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_analog_connector_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_analog_connector_ORD 2 #define DT_N_S_analog_connector_ORD_STR_SORTABLE 00002 /* Ordinals for what this node depends on directly: */ #define DT_N_S_analog_connector_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_analog_connector_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_analog_connector_EXISTS 1 #define DT_N_INST_0_arduino_uno_adc DT_N_S_analog_connector #define DT_N_NODELABEL_arduino_adc DT_N_S_analog_connector /* Macros for properties that are special in the specification: */ #define DT_N_S_analog_connector_REG_NUM 0 #define DT_N_S_analog_connector_RANGES_NUM 0 #define DT_N_S_analog_connector_FOREACH_RANGE(fn) #define DT_N_S_analog_connector_IRQ_NUM 0 #define DT_N_S_analog_connector_IRQ_LEVEL 0 #define DT_N_S_analog_connector_COMPAT_MATCHES_arduino_uno_adc 1 #define DT_N_S_analog_connector_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_analog_connector_COMPAT_VENDOR_IDX_0 "Arduino" #define DT_N_S_analog_connector_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_analog_connector_COMPAT_MODEL_IDX_0 "uno-adc" #define DT_N_S_analog_connector_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_analog_connector_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_analog_connector_P_wakeup_source 0 #define DT_N_S_analog_connector_P_wakeup_source_EXISTS 1 #define DT_N_S_analog_connector_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_analog_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_analog_connector_P_compatible {"arduino,uno-adc"} #define DT_N_S_analog_connector_P_compatible_IDX_0 "arduino,uno-adc" #define DT_N_S_analog_connector_P_compatible_IDX_0_STRING_UNQUOTED arduino,uno-adc #define DT_N_S_analog_connector_P_compatible_IDX_0_STRING_TOKEN arduino_uno_adc #define DT_N_S_analog_connector_P_compatible_IDX_0_STRING_UPPER_TOKEN ARDUINO_UNO_ADC #define DT_N_S_analog_connector_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_analog_connector, compatible, 0) #define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_analog_connector, compatible, 0) #define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_analog_connector, compatible, 0, __VA_ARGS__) #define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_analog_connector, compatible, 0, __VA_ARGS__) #define DT_N_S_analog_connector_P_compatible_LEN 1 #define DT_N_S_analog_connector_P_compatible_EXISTS 1 #define DT_N_S_analog_connector_P_zephyr_deferred_init 0 #define DT_N_S_analog_connector_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /chosen * * Node identifier: DT_N_S_chosen */ /* Node's full path: */ #define DT_N_S_chosen_PATH "/chosen" /* Node's name with unit-address: */ #define DT_N_S_chosen_FULL_NAME "chosen" /* Node parent (/) identifier: */ #define DT_N_S_chosen_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_chosen_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_chosen_CHILD_NUM 0 #define DT_N_S_chosen_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_chosen_FOREACH_CHILD(fn) #define DT_N_S_chosen_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_chosen_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_chosen_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_chosen_ORD 3 #define DT_N_S_chosen_ORD_STR_SORTABLE 00003 /* Ordinals for what this node depends on directly: */ #define DT_N_S_chosen_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_chosen_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_chosen_REG_NUM 0 #define DT_N_S_chosen_RANGES_NUM 0 #define DT_N_S_chosen_FOREACH_RANGE(fn) #define DT_N_S_chosen_IRQ_NUM 0 #define DT_N_S_chosen_IRQ_LEVEL 0 #define DT_N_S_chosen_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_chosen_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /connector * * Node identifier: DT_N_S_connector * * Binding (compatible = arduino-header-r3): * $ZEPHYR_BASE/dts/bindings/gpio/arduino-header-r3.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_connector_PATH "/connector" /* Node's name with unit-address: */ #define DT_N_S_connector_FULL_NAME "connector" /* Node parent (/) identifier: */ #define DT_N_S_connector_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_connector_CHILD_IDX 11 /* Helper macros for child nodes of this node. */ #define DT_N_S_connector_CHILD_NUM 0 #define DT_N_S_connector_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_connector_FOREACH_CHILD(fn) #define DT_N_S_connector_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_connector_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_connector_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_connector_ORD 4 #define DT_N_S_connector_ORD_STR_SORTABLE 00004 /* Ordinals for what this node depends on directly: */ #define DT_N_S_connector_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_connector_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_connector_EXISTS 1 #define DT_N_INST_0_arduino_header_r3 DT_N_S_connector #define DT_N_NODELABEL_arduino_header DT_N_S_connector /* Macros for properties that are special in the specification: */ #define DT_N_S_connector_REG_NUM 0 #define DT_N_S_connector_RANGES_NUM 0 #define DT_N_S_connector_FOREACH_RANGE(fn) #define DT_N_S_connector_IRQ_NUM 0 #define DT_N_S_connector_IRQ_LEVEL 0 #define DT_N_S_connector_COMPAT_MATCHES_arduino_header_r3 1 #define DT_N_S_connector_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_connector_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_connector_P_wakeup_source 0 #define DT_N_S_connector_P_wakeup_source_EXISTS 1 #define DT_N_S_connector_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_connector_P_compatible {"arduino-header-r3"} #define DT_N_S_connector_P_compatible_IDX_0 "arduino-header-r3" #define DT_N_S_connector_P_compatible_IDX_0_STRING_UNQUOTED arduino-header-r3 #define DT_N_S_connector_P_compatible_IDX_0_STRING_TOKEN arduino_header_r3 #define DT_N_S_connector_P_compatible_IDX_0_STRING_UPPER_TOKEN ARDUINO_HEADER_R3 #define DT_N_S_connector_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, compatible, 0) #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, compatible, 0) #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__) #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__) #define DT_N_S_connector_P_compatible_LEN 1 #define DT_N_S_connector_P_compatible_EXISTS 1 #define DT_N_S_connector_P_zephyr_deferred_init 0 #define DT_N_S_connector_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /entropy_bt_hci * * Node identifier: DT_N_S_entropy_bt_hci * * Binding (compatible = zephyr,bt-hci-entropy): * $ZEPHYR_BASE/dts/bindings/bluetooth/zephyr,bt-hci-entropy.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_entropy_bt_hci_PATH "/entropy_bt_hci" /* Node's name with unit-address: */ #define DT_N_S_entropy_bt_hci_FULL_NAME "entropy_bt_hci" /* Node parent (/) identifier: */ #define DT_N_S_entropy_bt_hci_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_entropy_bt_hci_CHILD_IDX 4 /* Helper macros for child nodes of this node. */ #define DT_N_S_entropy_bt_hci_CHILD_NUM 0 #define DT_N_S_entropy_bt_hci_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_entropy_bt_hci_FOREACH_CHILD(fn) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_entropy_bt_hci_ORD 5 #define DT_N_S_entropy_bt_hci_ORD_STR_SORTABLE 00005 /* Ordinals for what this node depends on directly: */ #define DT_N_S_entropy_bt_hci_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_entropy_bt_hci_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_entropy_bt_hci_EXISTS 1 #define DT_N_INST_0_zephyr_bt_hci_entropy DT_N_S_entropy_bt_hci #define DT_N_NODELABEL_rng_hci DT_N_S_entropy_bt_hci /* Macros for properties that are special in the specification: */ #define DT_N_S_entropy_bt_hci_REG_NUM 0 #define DT_N_S_entropy_bt_hci_RANGES_NUM 0 #define DT_N_S_entropy_bt_hci_FOREACH_RANGE(fn) #define DT_N_S_entropy_bt_hci_IRQ_NUM 0 #define DT_N_S_entropy_bt_hci_IRQ_LEVEL 0 #define DT_N_S_entropy_bt_hci_COMPAT_MATCHES_zephyr_bt_hci_entropy 1 #define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding" #define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0 "bt-hci-entropy" #define DT_N_S_entropy_bt_hci_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_entropy_bt_hci_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_entropy_bt_hci_P_wakeup_source 0 #define DT_N_S_entropy_bt_hci_P_wakeup_source_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_entropy_bt_hci_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_status "okay" #define DT_N_S_entropy_bt_hci_P_status_STRING_UNQUOTED okay #define DT_N_S_entropy_bt_hci_P_status_STRING_TOKEN okay #define DT_N_S_entropy_bt_hci_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_entropy_bt_hci_P_status_IDX_0 "okay" #define DT_N_S_entropy_bt_hci_P_status_IDX_0_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_status_ENUM_IDX 1 #define DT_N_S_entropy_bt_hci_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_status_ENUM_TOKEN okay #define DT_N_S_entropy_bt_hci_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, status, 0) #define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, status, 0) #define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__) #define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__) #define DT_N_S_entropy_bt_hci_P_status_LEN 1 #define DT_N_S_entropy_bt_hci_P_status_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_compatible {"zephyr,bt-hci-entropy"} #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0 "zephyr,bt-hci-entropy" #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UNQUOTED zephyr,bt-hci-entropy #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_TOKEN zephyr_bt_hci_entropy #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_BT_HCI_ENTROPY #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, compatible, 0) #define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, compatible, 0) #define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__) #define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__) #define DT_N_S_entropy_bt_hci_P_compatible_LEN 1 #define DT_N_S_entropy_bt_hci_P_compatible_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_zephyr_deferred_init 0 #define DT_N_S_entropy_bt_hci_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc * * Node identifier: DT_N_S_soc */ /* Node's full path: */ #define DT_N_S_soc_PATH "/soc" /* Node's name with unit-address: */ #define DT_N_S_soc_FULL_NAME "soc" /* Node parent (/) identifier: */ #define DT_N_S_soc_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_soc_CHILD_IDX 2 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_CHILD_NUM 11 #define DT_N_S_soc_CHILD_NUM_STATUS_OKAY 9 #define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_crypto_50840000) fn(DT_N_S_soc_S_ctrlap_50006000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_gpiote_40031000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) #define DT_N_S_soc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50840000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ctrlap_50006000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_40031000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000) #define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__) fn(DT_N_S_soc_S_ctrlap_50006000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_40031000, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) #define DT_N_S_soc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ctrlap_50006000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_40031000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_crypto_50840000) fn(DT_N_S_soc_S_ctrlap_50006000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50840000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ctrlap_50006000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000) #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__) fn(DT_N_S_soc_S_ctrlap_50006000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ctrlap_50006000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_ORD 6 #define DT_N_S_soc_ORD_STR_SORTABLE 00006 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_SUPPORTS_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 8, /* /soc/gpiote@5000d000 */ \ 9, /* /soc/peripheral@50000000 */ \ 57, /* /soc/crypto@50840000 */ \ 58, /* /soc/ctrlap@50006000 */ \ 59, /* /soc/ficr@ff0000 */ \ 60, /* /soc/gpiote@40031000 */ \ 61, /* /soc/memory@20000000 */ \ 62, /* /soc/spu@50003000 */ \ 63, /* /soc/timer@e000e010 */ \ 64, /* /soc/uicr@ff8000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_EXISTS 1 #define DT_N_INST_0_nordic_nrf9161_laca DT_N_S_soc #define DT_N_INST_0_nordic_nrf9120 DT_N_S_soc #define DT_N_INST_0_nordic_nrf91 DT_N_S_soc #define DT_N_INST_0_simple_bus DT_N_S_soc /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_REG_NUM 0 #define DT_N_S_soc_RANGES_NUM 0 #define DT_N_S_soc_FOREACH_RANGE(fn) #define DT_N_S_soc_IRQ_NUM 0 #define DT_N_S_soc_IRQ_LEVEL 0 #define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf9161_laca 1 #define DT_N_S_soc_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_COMPAT_MODEL_IDX_0 "nrf9161-laca" #define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf9120 1 #define DT_N_S_soc_COMPAT_VENDOR_IDX_1_EXISTS 1 #define DT_N_S_soc_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor" #define DT_N_S_soc_COMPAT_MODEL_IDX_1_EXISTS 1 #define DT_N_S_soc_COMPAT_MODEL_IDX_1 "nrf9120" #define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf91 1 #define DT_N_S_soc_COMPAT_VENDOR_IDX_2_EXISTS 1 #define DT_N_S_soc_COMPAT_VENDOR_IDX_2 "Nordic Semiconductor" #define DT_N_S_soc_COMPAT_MODEL_IDX_2_EXISTS 1 #define DT_N_S_soc_COMPAT_MODEL_IDX_2 "nrf91" #define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1 #define DT_N_S_soc_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_P_compatible {"nordic,nrf9161-laca", "nordic,nrf9120", "nordic,nrf91", "simple-bus"} #define DT_N_S_soc_P_compatible_IDX_0 "nordic,nrf9161-laca" #define DT_N_S_soc_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf9161-laca #define DT_N_S_soc_P_compatible_IDX_0_STRING_TOKEN nordic_nrf9161_laca #define DT_N_S_soc_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF9161_LACA #define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_P_compatible_IDX_1 "nordic,nrf9120" #define DT_N_S_soc_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf9120 #define DT_N_S_soc_P_compatible_IDX_1_STRING_TOKEN nordic_nrf9120 #define DT_N_S_soc_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF9120 #define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_P_compatible_IDX_2 "nordic,nrf91" #define DT_N_S_soc_P_compatible_IDX_2_STRING_UNQUOTED nordic,nrf91 #define DT_N_S_soc_P_compatible_IDX_2_STRING_TOKEN nordic_nrf91 #define DT_N_S_soc_P_compatible_IDX_2_STRING_UPPER_TOKEN NORDIC_NRF91 #define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_P_compatible_IDX_3 "simple-bus" #define DT_N_S_soc_P_compatible_IDX_3_STRING_UNQUOTED simple-bus #define DT_N_S_soc_P_compatible_IDX_3_STRING_TOKEN simple_bus #define DT_N_S_soc_P_compatible_IDX_3_STRING_UPPER_TOKEN SIMPLE_BUS #define DT_N_S_soc_P_compatible_IDX_3_EXISTS 1 #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc, compatible, 0) \ fn(DT_N_S_soc, compatible, 1) \ fn(DT_N_S_soc, compatible, 2) \ fn(DT_N_S_soc, compatible, 3) #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc, compatible, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc, compatible, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc, compatible, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc, compatible, 3) #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) \ fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) \ fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) \ fn(DT_N_S_soc, compatible, 3, __VA_ARGS__) #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc, compatible, 3, __VA_ARGS__) #define DT_N_S_soc_P_compatible_LEN 4 #define DT_N_S_soc_P_compatible_EXISTS 1 #define DT_N_S_soc_P_ranges_EXISTS 1 /* * Devicetree node: /soc/interrupt-controller@e000e100 * * Node identifier: DT_N_S_soc_S_interrupt_controller_e000e100 * * Binding (compatible = arm,v8m-nvic): * $ZEPHYR_BASE/dts/bindings/interrupt-controller/arm,v8m-nvic.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_PATH "/soc/interrupt-controller@e000e100" /* Node's name with unit-address: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME "interrupt-controller@e000e100" /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_NUM 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD(fn) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_ORD 7 #define DT_N_S_soc_S_interrupt_controller_e000e100_ORD_STR_SORTABLE 00007 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS \ 6, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS \ 8, /* /soc/gpiote@5000d000 */ \ 12, /* /soc/peripheral@50000000/timer@10000 */ \ 50, /* /soc/peripheral@50000000/pwm@21000 */ \ 57, /* /soc/crypto@50840000 */ \ 60, /* /soc/gpiote@40031000 */ \ 62, /* /soc/spu@50003000 */ \ 65, /* /soc/peripheral@50000000/adc@e000 */ \ 66, /* /soc/peripheral@50000000/clock@5000 */ \ 68, /* /soc/peripheral@50000000/egu@1b000 */ \ 69, /* /soc/peripheral@50000000/egu@1c000 */ \ 70, /* /soc/peripheral@50000000/egu@1d000 */ \ 71, /* /soc/peripheral@50000000/egu@1e000 */ \ 72, /* /soc/peripheral@50000000/egu@1f000 */ \ 73, /* /soc/peripheral@50000000/egu@20000 */ \ 74, /* /soc/peripheral@50000000/i2c@8000 */ \ 75, /* /soc/peripheral@50000000/i2c@9000 */ \ 76, /* /soc/peripheral@50000000/i2c@b000 */ \ 77, /* /soc/peripheral@50000000/i2s@28000 */ \ 78, /* /soc/peripheral@50000000/ipc@2a000 */ \ 79, /* /soc/peripheral@50000000/kmu@39000 */ \ 80, /* /soc/peripheral@50000000/pdm@26000 */ \ 81, /* /soc/peripheral@50000000/pwm@22000 */ \ 82, /* /soc/peripheral@50000000/pwm@23000 */ \ 83, /* /soc/peripheral@50000000/pwm@24000 */ \ 85, /* /soc/peripheral@50000000/rtc@14000 */ \ 86, /* /soc/peripheral@50000000/rtc@15000 */ \ 87, /* /soc/peripheral@50000000/spi@8000 */ \ 88, /* /soc/peripheral@50000000/spi@9000 */ \ 89, /* /soc/peripheral@50000000/spi@a000 */ \ 90, /* /soc/peripheral@50000000/timer@f000 */ \ 91, /* /soc/peripheral@50000000/timer@11000 */ \ 92, /* /soc/peripheral@50000000/uart@8000 */ \ 93, /* /soc/peripheral@50000000/uart@9000 */ \ 94, /* /soc/peripheral@50000000/uart@a000 */ \ 95, /* /soc/peripheral@50000000/uart@b000 */ \ 97, /* /soc/peripheral@50000000/watchdog@18000 */ \ 107, /* /soc/peripheral@50000000/i2c@a000 */ \ 109, /* /soc/peripheral@50000000/power@5000 */ \ 112, /* /soc/peripheral@50000000/spi@b000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1 #define DT_N_INST_0_arm_v8m_nvic DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_NODELABEL_nvic DT_N_S_soc_S_interrupt_controller_e000e100 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */ #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */ #define DT_N_S_soc_S_interrupt_controller_e000e100_RANGES_NUM 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_RANGE(fn) #define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_LEVEL 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v8m_nvic 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0 "ARM Ltd." #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0 "v8m-nvic" #define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible {"arm,v8m-nvic"} #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v8m-nvic" #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UNQUOTED arm,v8m-nvic #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_TOKEN arm_v8m_nvic #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_V8M_NVIC #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0) #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0) #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */} #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 3 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1 /* * Devicetree node: /soc/gpiote@5000d000 * * Node identifier: DT_N_S_soc_S_gpiote_5000d000 * * Binding (compatible = nordic,nrf-gpiote): * $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpiote.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_gpiote_5000d000_PATH "/soc/gpiote@5000d000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_gpiote_5000d000_FULL_NAME "gpiote@5000d000" /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_gpiote_5000d000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_gpiote_5000d000_CHILD_IDX 6 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_gpiote_5000d000_CHILD_NUM 0 #define DT_N_S_soc_S_gpiote_5000d000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_gpiote_5000d000_ORD 8 #define DT_N_S_soc_S_gpiote_5000d000_ORD_STR_SORTABLE 00008 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_gpiote_5000d000_REQUIRES_ORDS \ 6, /* /soc */ \ 7, /* /soc/interrupt-controller@e000e100 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_gpiote_5000d000_SUPPORTS_ORDS \ 10, /* /soc/peripheral@50000000/gpio@842500 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_gpiote_5000d000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_5000d000 #define DT_N_NODELABEL_gpiote DT_N_S_soc_S_gpiote_5000d000 #define DT_N_NODELABEL_gpiote0 DT_N_S_soc_S_gpiote_5000d000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_gpiote_5000d000_REG_NUM 1 #define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_VAL_ADDRESS 1342230528 /* 0x5000d000 */ #define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_gpiote_5000d000_RANGES_NUM 0 #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_gpiote_5000d000_IRQ_NUM 1 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_irq 13 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_priority 5 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_LEVEL 1 #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MATCHES_nordic_nrf_gpiote 1 #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MODEL_IDX_0 "nrf-gpiote" #define DT_N_S_soc_S_gpiote_5000d000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_gpiote_5000d000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_gpiote_5000d000_P_wakeup_source 0 #define DT_N_S_soc_S_gpiote_5000d000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_status "okay" #define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_gpiote_5000d000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_gpiote_5000d000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0) #define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0) #define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_5000d000_P_status_LEN 1 #define DT_N_S_soc_S_gpiote_5000d000_P_status_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_compatible {"nordic,nrf-gpiote"} #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0 "nordic,nrf-gpiote" #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpiote #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpiote #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIOTE #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0) #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0) #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_LEN 1 #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_reg {1342230528 /* 0x5000d000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_0 1342230528 #define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_reg_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts {13 /* 0xd */, 5 /* 0x5 */} #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_0 13 #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_1 5 #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_instance 0 #define DT_N_S_soc_S_gpiote_5000d000_P_instance_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000 */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_PATH "/soc/peripheral@50000000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_FULL_NAME "peripheral@50000000" /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_CHILD_IDX 3 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_CHILD_NUM 40 #define DT_N_S_soc_S_peripheral_50000000_CHILD_NUM_STATUS_OKAY 22 #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_ORD 9 #define DT_N_S_soc_S_peripheral_50000000_ORD_STR_SORTABLE 00009 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_REQUIRES_ORDS \ 6, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_SUPPORTS_ORDS \ 10, /* /soc/peripheral@50000000/gpio@842500 */ \ 12, /* /soc/peripheral@50000000/timer@10000 */ \ 50, /* /soc/peripheral@50000000/pwm@21000 */ \ 65, /* /soc/peripheral@50000000/adc@e000 */ \ 66, /* /soc/peripheral@50000000/clock@5000 */ \ 67, /* /soc/peripheral@50000000/dppic@17000 */ \ 68, /* /soc/peripheral@50000000/egu@1b000 */ \ 69, /* /soc/peripheral@50000000/egu@1c000 */ \ 70, /* /soc/peripheral@50000000/egu@1d000 */ \ 71, /* /soc/peripheral@50000000/egu@1e000 */ \ 72, /* /soc/peripheral@50000000/egu@1f000 */ \ 73, /* /soc/peripheral@50000000/egu@20000 */ \ 74, /* /soc/peripheral@50000000/i2c@8000 */ \ 75, /* /soc/peripheral@50000000/i2c@9000 */ \ 76, /* /soc/peripheral@50000000/i2c@b000 */ \ 77, /* /soc/peripheral@50000000/i2s@28000 */ \ 78, /* /soc/peripheral@50000000/ipc@2a000 */ \ 79, /* /soc/peripheral@50000000/kmu@39000 */ \ 80, /* /soc/peripheral@50000000/pdm@26000 */ \ 81, /* /soc/peripheral@50000000/pwm@22000 */ \ 82, /* /soc/peripheral@50000000/pwm@23000 */ \ 83, /* /soc/peripheral@50000000/pwm@24000 */ \ 84, /* /soc/peripheral@50000000/regulator@4000 */ \ 85, /* /soc/peripheral@50000000/rtc@14000 */ \ 86, /* /soc/peripheral@50000000/rtc@15000 */ \ 87, /* /soc/peripheral@50000000/spi@8000 */ \ 88, /* /soc/peripheral@50000000/spi@9000 */ \ 89, /* /soc/peripheral@50000000/spi@a000 */ \ 90, /* /soc/peripheral@50000000/timer@f000 */ \ 91, /* /soc/peripheral@50000000/timer@11000 */ \ 92, /* /soc/peripheral@50000000/uart@8000 */ \ 93, /* /soc/peripheral@50000000/uart@9000 */ \ 94, /* /soc/peripheral@50000000/uart@a000 */ \ 95, /* /soc/peripheral@50000000/uart@b000 */ \ 96, /* /soc/peripheral@50000000/vmc@3a000 */ \ 97, /* /soc/peripheral@50000000/watchdog@18000 */ \ 98, /* /soc/peripheral@50000000/flash-controller@39000 */ \ 107, /* /soc/peripheral@50000000/i2c@a000 */ \ 109, /* /soc/peripheral@50000000/power@5000 */ \ 112, /* /soc/peripheral@50000000/spi@b000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_REG_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_RANGES_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */ #define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 1342177280 /* 0x50000000 */ #define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_LENGTH 268435456 /* 0x10000000 */ #define DT_N_S_soc_S_peripheral_50000000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_peripheral_50000000, 0) #define DT_N_S_soc_S_peripheral_50000000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_P_ranges_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/gpio@842500 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 * * Binding (compatible = nordic,nrf-gpio): * $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpio.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PATH "/soc/peripheral@50000000/gpio@842500" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FULL_NAME "gpio@842500" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_CHILD_IDX 31 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_ORD 10 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_ORD_STR_SORTABLE 00010 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REQUIRES_ORDS \ 8, /* /soc/gpiote@5000d000 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_SUPPORTS_ORDS \ 11, /* /gpio-reset */ \ 14, /* /buttons */ \ 15, /* /buttons/button_0 */ \ 16, /* /buttons/button_1 */ \ 17, /* /buttons/button_2 */ \ 18, /* /buttons/button_3 */ \ 22, /* /leds */ \ 23, /* /leds/led_0 */ \ 24, /* /leds/led_1 */ \ 25, /* /leds/led_2 */ \ 26, /* /leds/led_3 */ \ 108, /* /soc/peripheral@50000000/i2c@a000/pcal6408a@21 */ \ 112, /* /soc/peripheral@50000000/spi@b000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_EXISTS 1 #define DT_N_INST_0_nordic_nrf_gpio DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_NODELABEL_gpio0 DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_VAL_ADDRESS 1350837504 /* 0x50842500 */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_VAL_SIZE 768 /* 0x300 */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MATCHES_nordic_nrf_gpio 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MODEL_IDX_0 "nrf-gpio" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpio_controller 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpio_controller_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_ngpios 32 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_ngpios_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible {"nordic,nrf-gpio"} #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0 "nordic,nrf-gpio" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg {8660224 /* 0x842500 */, 768 /* 0x300 */} #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_0 8660224 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_1 768 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance DT_N_S_soc_S_gpiote_5000d000 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_IDX_0 DT_N_S_soc_S_gpiote_5000d000 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_IDX_0_PH DT_N_S_soc_S_gpiote_5000d000 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, gpiote_instance, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, gpiote_instance, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, gpiote_instance, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, gpiote_instance, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_port 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_port_EXISTS 1 /* * Devicetree node: /gpio-reset * * Node identifier: DT_N_S_gpio_reset * * Binding (compatible = nordic,nrf9161dk-nrf5340-reset): * $ZEPHYR_BASE/boards/nordic/nrf9161dk/dts/bindings/nordic,nrf9161dk-nrf5340-reset.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_gpio_reset_PATH "/gpio-reset" /* Node's name with unit-address: */ #define DT_N_S_gpio_reset_FULL_NAME "gpio-reset" /* Node parent (/) identifier: */ #define DT_N_S_gpio_reset_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_gpio_reset_CHILD_IDX 10 /* Helper macros for child nodes of this node. */ #define DT_N_S_gpio_reset_CHILD_NUM 0 #define DT_N_S_gpio_reset_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_gpio_reset_FOREACH_CHILD(fn) #define DT_N_S_gpio_reset_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_gpio_reset_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_gpio_reset_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_gpio_reset_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_gpio_reset_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_gpio_reset_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_gpio_reset_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_gpio_reset_ORD 11 #define DT_N_S_gpio_reset_ORD_STR_SORTABLE 00011 /* Ordinals for what this node depends on directly: */ #define DT_N_S_gpio_reset_REQUIRES_ORDS \ 0, /* / */ \ 10, /* /soc/peripheral@50000000/gpio@842500 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_gpio_reset_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_gpio_reset_EXISTS 1 #define DT_N_INST_0_nordic_nrf9161dk_nrf5340_reset DT_N_S_gpio_reset #define DT_N_NODELABEL_nrf5340_reset DT_N_S_gpio_reset /* Macros for properties that are special in the specification: */ #define DT_N_S_gpio_reset_REG_NUM 0 #define DT_N_S_gpio_reset_RANGES_NUM 0 #define DT_N_S_gpio_reset_FOREACH_RANGE(fn) #define DT_N_S_gpio_reset_IRQ_NUM 0 #define DT_N_S_gpio_reset_IRQ_LEVEL 0 #define DT_N_S_gpio_reset_COMPAT_MATCHES_nordic_nrf9161dk_nrf5340_reset 1 #define DT_N_S_gpio_reset_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_gpio_reset_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_gpio_reset_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_gpio_reset_COMPAT_MODEL_IDX_0 "nrf9161dk-nrf5340-reset" #define DT_N_S_gpio_reset_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_gpio_reset_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_gpio_reset_P_wakeup_source 0 #define DT_N_S_gpio_reset_P_wakeup_source_EXISTS 1 #define DT_N_S_gpio_reset_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_gpio_reset_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_gpio_reset_P_status "disabled" #define DT_N_S_gpio_reset_P_status_STRING_UNQUOTED disabled #define DT_N_S_gpio_reset_P_status_STRING_TOKEN disabled #define DT_N_S_gpio_reset_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_gpio_reset_P_status_IDX_0 "disabled" #define DT_N_S_gpio_reset_P_status_IDX_0_EXISTS 1 #define DT_N_S_gpio_reset_P_status_ENUM_IDX 2 #define DT_N_S_gpio_reset_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_gpio_reset_P_status_ENUM_TOKEN disabled #define DT_N_S_gpio_reset_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_gpio_reset_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_reset, status, 0) #define DT_N_S_gpio_reset_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_reset, status, 0) #define DT_N_S_gpio_reset_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_reset, status, 0, __VA_ARGS__) #define DT_N_S_gpio_reset_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_reset, status, 0, __VA_ARGS__) #define DT_N_S_gpio_reset_P_status_LEN 1 #define DT_N_S_gpio_reset_P_status_EXISTS 1 #define DT_N_S_gpio_reset_P_compatible {"nordic,nrf9161dk-nrf5340-reset"} #define DT_N_S_gpio_reset_P_compatible_IDX_0 "nordic,nrf9161dk-nrf5340-reset" #define DT_N_S_gpio_reset_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf9161dk-nrf5340-reset #define DT_N_S_gpio_reset_P_compatible_IDX_0_STRING_TOKEN nordic_nrf9161dk_nrf5340_reset #define DT_N_S_gpio_reset_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF9161DK_NRF5340_RESET #define DT_N_S_gpio_reset_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_gpio_reset_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_reset, compatible, 0) #define DT_N_S_gpio_reset_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_reset, compatible, 0) #define DT_N_S_gpio_reset_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_reset, compatible, 0, __VA_ARGS__) #define DT_N_S_gpio_reset_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_reset, compatible, 0, __VA_ARGS__) #define DT_N_S_gpio_reset_P_compatible_LEN 1 #define DT_N_S_gpio_reset_P_compatible_EXISTS 1 #define DT_N_S_gpio_reset_P_zephyr_deferred_init 0 #define DT_N_S_gpio_reset_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_gpio_reset_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_gpio_reset_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_gpio_reset_P_gpios_IDX_0_VAL_pin 21 #define DT_N_S_gpio_reset_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_gpio_reset_P_gpios_IDX_0_VAL_flags 1 #define DT_N_S_gpio_reset_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_gpio_reset_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_reset, gpios, 0) #define DT_N_S_gpio_reset_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_reset, gpios, 0) #define DT_N_S_gpio_reset_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_reset, gpios, 0, __VA_ARGS__) #define DT_N_S_gpio_reset_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_reset, gpios, 0, __VA_ARGS__) #define DT_N_S_gpio_reset_P_gpios_LEN 1 #define DT_N_S_gpio_reset_P_gpios_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/timer@10000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_10000 * * Binding (compatible = nordic,nrf-timer): * $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PATH "/soc/peripheral@50000000/timer@10000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FULL_NAME "timer@10000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_CHILD_IDX 38 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_ORD 12 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_ORD_STR_SORTABLE 00012 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_SUPPORTS_ORDS \ 13, /* /sw-pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_10000 #define DT_N_NODELABEL_timer1 DT_N_S_soc_S_peripheral_50000000_S_timer_10000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_VAL_ADDRESS 1342242816 /* 0x50010000 */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_irq 16 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MATCHES_nordic_nrf_timer 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MODEL_IDX_0 "nrf-timer" #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible {"nordic,nrf-timer"} #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0 "nordic,nrf-timer" #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg {65536 /* 0x10000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_0 65536 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts {16 /* 0x10 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_0 16 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_cc_num 6 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_cc_num_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_bit_width 32 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_bit_width_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_frequency 16000000 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_prescaler 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_prescaler_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zli 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zli_EXISTS 1 /* * Devicetree node: /sw-pwm * * Node identifier: DT_N_S_sw_pwm * * Binding (compatible = nordic,nrf-sw-pwm): * $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-sw-pwm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_sw_pwm_PATH "/sw-pwm" /* Node's name with unit-address: */ #define DT_N_S_sw_pwm_FULL_NAME "sw-pwm" /* Node parent (/) identifier: */ #define DT_N_S_sw_pwm_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_sw_pwm_CHILD_IDX 5 /* Helper macros for child nodes of this node. */ #define DT_N_S_sw_pwm_CHILD_NUM 0 #define DT_N_S_sw_pwm_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_sw_pwm_FOREACH_CHILD(fn) #define DT_N_S_sw_pwm_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_sw_pwm_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_sw_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_sw_pwm_ORD 13 #define DT_N_S_sw_pwm_ORD_STR_SORTABLE 00013 /* Ordinals for what this node depends on directly: */ #define DT_N_S_sw_pwm_REQUIRES_ORDS \ 0, /* / */ \ 12, /* /soc/peripheral@50000000/timer@10000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_sw_pwm_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_sw_pwm_EXISTS 1 #define DT_N_INST_0_nordic_nrf_sw_pwm DT_N_S_sw_pwm #define DT_N_NODELABEL_sw_pwm DT_N_S_sw_pwm /* Macros for properties that are special in the specification: */ #define DT_N_S_sw_pwm_REG_NUM 0 #define DT_N_S_sw_pwm_RANGES_NUM 0 #define DT_N_S_sw_pwm_FOREACH_RANGE(fn) #define DT_N_S_sw_pwm_IRQ_NUM 0 #define DT_N_S_sw_pwm_IRQ_LEVEL 0 #define DT_N_S_sw_pwm_COMPAT_MATCHES_nordic_nrf_sw_pwm 1 #define DT_N_S_sw_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_sw_pwm_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_sw_pwm_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_sw_pwm_COMPAT_MODEL_IDX_0 "nrf-sw-pwm" #define DT_N_S_sw_pwm_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_sw_pwm_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_sw_pwm_P_wakeup_source 0 #define DT_N_S_sw_pwm_P_wakeup_source_EXISTS 1 #define DT_N_S_sw_pwm_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_sw_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_sw_pwm_P_status "disabled" #define DT_N_S_sw_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_sw_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_sw_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_sw_pwm_P_status_IDX_0 "disabled" #define DT_N_S_sw_pwm_P_status_IDX_0_EXISTS 1 #define DT_N_S_sw_pwm_P_status_ENUM_IDX 2 #define DT_N_S_sw_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_sw_pwm_P_status_ENUM_TOKEN disabled #define DT_N_S_sw_pwm_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sw_pwm, status, 0) #define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sw_pwm, status, 0) #define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sw_pwm, status, 0, __VA_ARGS__) #define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sw_pwm, status, 0, __VA_ARGS__) #define DT_N_S_sw_pwm_P_status_LEN 1 #define DT_N_S_sw_pwm_P_status_EXISTS 1 #define DT_N_S_sw_pwm_P_compatible {"nordic,nrf-sw-pwm"} #define DT_N_S_sw_pwm_P_compatible_IDX_0 "nordic,nrf-sw-pwm" #define DT_N_S_sw_pwm_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-sw-pwm #define DT_N_S_sw_pwm_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_sw_pwm #define DT_N_S_sw_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SW_PWM #define DT_N_S_sw_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sw_pwm, compatible, 0) #define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sw_pwm, compatible, 0) #define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sw_pwm, compatible, 0, __VA_ARGS__) #define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sw_pwm, compatible, 0, __VA_ARGS__) #define DT_N_S_sw_pwm_P_compatible_LEN 1 #define DT_N_S_sw_pwm_P_compatible_EXISTS 1 #define DT_N_S_sw_pwm_P_zephyr_deferred_init 0 #define DT_N_S_sw_pwm_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_sw_pwm_P_generator DT_N_S_soc_S_peripheral_50000000_S_timer_10000 #define DT_N_S_sw_pwm_P_generator_IDX_0 DT_N_S_soc_S_peripheral_50000000_S_timer_10000 #define DT_N_S_sw_pwm_P_generator_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_timer_10000 #define DT_N_S_sw_pwm_P_generator_IDX_0_EXISTS 1 #define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sw_pwm, generator, 0) #define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sw_pwm, generator, 0) #define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sw_pwm, generator, 0, __VA_ARGS__) #define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sw_pwm, generator, 0, __VA_ARGS__) #define DT_N_S_sw_pwm_P_generator_LEN 1 #define DT_N_S_sw_pwm_P_generator_EXISTS 1 #define DT_N_S_sw_pwm_P_clock_prescaler 0 #define DT_N_S_sw_pwm_P_clock_prescaler_EXISTS 1 /* * Devicetree node: /buttons * * Node identifier: DT_N_S_buttons * * Binding (compatible = gpio-keys): * $ZEPHYR_BASE/dts/bindings/input/gpio-keys.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_buttons_PATH "/buttons" /* Node's name with unit-address: */ #define DT_N_S_buttons_FULL_NAME "buttons" /* Node parent (/) identifier: */ #define DT_N_S_buttons_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_buttons_CHILD_IDX 9 /* Helper macros for child nodes of this node. */ #define DT_N_S_buttons_CHILD_NUM 4 #define DT_N_S_buttons_CHILD_NUM_STATUS_OKAY 4 #define DT_N_S_buttons_FOREACH_CHILD(fn) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) #define DT_N_S_buttons_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3) #define DT_N_S_buttons_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) #define DT_N_S_buttons_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) #define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) #define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3) #define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) #define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_buttons_ORD 14 #define DT_N_S_buttons_ORD_STR_SORTABLE 00014 /* Ordinals for what this node depends on directly: */ #define DT_N_S_buttons_REQUIRES_ORDS \ 0, /* / */ \ 10, /* /soc/peripheral@50000000/gpio@842500 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_buttons_SUPPORTS_ORDS \ 15, /* /buttons/button_0 */ \ 16, /* /buttons/button_1 */ \ 17, /* /buttons/button_2 */ \ 18, /* /buttons/button_3 */ /* Existence and alternate IDs: */ #define DT_N_S_buttons_EXISTS 1 #define DT_N_INST_0_gpio_keys DT_N_S_buttons /* Macros for properties that are special in the specification: */ #define DT_N_S_buttons_REG_NUM 0 #define DT_N_S_buttons_RANGES_NUM 0 #define DT_N_S_buttons_FOREACH_RANGE(fn) #define DT_N_S_buttons_IRQ_NUM 0 #define DT_N_S_buttons_IRQ_LEVEL 0 #define DT_N_S_buttons_COMPAT_MATCHES_gpio_keys 1 #define DT_N_S_buttons_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_buttons_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_buttons_P_wakeup_source 0 #define DT_N_S_buttons_P_wakeup_source_EXISTS 1 #define DT_N_S_buttons_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_buttons_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_buttons_P_compatible {"gpio-keys"} #define DT_N_S_buttons_P_compatible_IDX_0 "gpio-keys" #define DT_N_S_buttons_P_compatible_IDX_0_STRING_UNQUOTED gpio-keys #define DT_N_S_buttons_P_compatible_IDX_0_STRING_TOKEN gpio_keys #define DT_N_S_buttons_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_KEYS #define DT_N_S_buttons_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons, compatible, 0) #define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons, compatible, 0) #define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons, compatible, 0, __VA_ARGS__) #define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons, compatible, 0, __VA_ARGS__) #define DT_N_S_buttons_P_compatible_LEN 1 #define DT_N_S_buttons_P_compatible_EXISTS 1 #define DT_N_S_buttons_P_zephyr_deferred_init 0 #define DT_N_S_buttons_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_buttons_P_debounce_interval_ms 30 #define DT_N_S_buttons_P_debounce_interval_ms_EXISTS 1 #define DT_N_S_buttons_P_polling_mode 0 #define DT_N_S_buttons_P_polling_mode_EXISTS 1 /* * Devicetree node: /buttons/button_0 * * Node identifier: DT_N_S_buttons_S_button_0 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_buttons_S_button_0_PATH "/buttons/button_0" /* Node's name with unit-address: */ #define DT_N_S_buttons_S_button_0_FULL_NAME "button_0" /* Node parent (/buttons) identifier: */ #define DT_N_S_buttons_S_button_0_PARENT DT_N_S_buttons /* Node's index in its parent's list of children: */ #define DT_N_S_buttons_S_button_0_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_buttons_S_button_0_CHILD_NUM 0 #define DT_N_S_buttons_S_button_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_buttons_S_button_0_FOREACH_CHILD(fn) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_buttons_S_button_0_ORD 15 #define DT_N_S_buttons_S_button_0_ORD_STR_SORTABLE 00015 /* Ordinals for what this node depends on directly: */ #define DT_N_S_buttons_S_button_0_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000/gpio@842500 */ \ 14, /* /buttons */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_buttons_S_button_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_buttons_S_button_0_EXISTS 1 #define DT_N_ALIAS_sw0 DT_N_S_buttons_S_button_0 #define DT_N_ALIAS_mcuboot_button0 DT_N_S_buttons_S_button_0 #define DT_N_NODELABEL_button0 DT_N_S_buttons_S_button_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_buttons_S_button_0_REG_NUM 0 #define DT_N_S_buttons_S_button_0_RANGES_NUM 0 #define DT_N_S_buttons_S_button_0_FOREACH_RANGE(fn) #define DT_N_S_buttons_S_button_0_IRQ_NUM 0 #define DT_N_S_buttons_S_button_0_IRQ_LEVEL 0 #define DT_N_S_buttons_S_button_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_buttons_S_button_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin 8 #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags 17 #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_0, gpios, 0) #define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0, gpios, 0) #define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_0_P_gpios_LEN 1 #define DT_N_S_buttons_S_button_0_P_gpios_EXISTS 1 #define DT_N_S_buttons_S_button_0_P_label "Push button 1" #define DT_N_S_buttons_S_button_0_P_label_STRING_UNQUOTED Push button 1 #define DT_N_S_buttons_S_button_0_P_label_STRING_TOKEN Push_button_1 #define DT_N_S_buttons_S_button_0_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_1 #define DT_N_S_buttons_S_button_0_P_label_IDX_0 "Push button 1" #define DT_N_S_buttons_S_button_0_P_label_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_0, label, 0) #define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0, label, 0) #define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_0_P_label_LEN 1 #define DT_N_S_buttons_S_button_0_P_label_EXISTS 1 #define DT_N_S_buttons_S_button_0_P_zephyr_code 11 #define DT_N_S_buttons_S_button_0_P_zephyr_code_EXISTS 1 /* * Devicetree node: /buttons/button_1 * * Node identifier: DT_N_S_buttons_S_button_1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_buttons_S_button_1_PATH "/buttons/button_1" /* Node's name with unit-address: */ #define DT_N_S_buttons_S_button_1_FULL_NAME "button_1" /* Node parent (/buttons) identifier: */ #define DT_N_S_buttons_S_button_1_PARENT DT_N_S_buttons /* Node's index in its parent's list of children: */ #define DT_N_S_buttons_S_button_1_CHILD_IDX 1 /* Helper macros for child nodes of this node. */ #define DT_N_S_buttons_S_button_1_CHILD_NUM 0 #define DT_N_S_buttons_S_button_1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_buttons_S_button_1_FOREACH_CHILD(fn) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_buttons_S_button_1_ORD 16 #define DT_N_S_buttons_S_button_1_ORD_STR_SORTABLE 00016 /* Ordinals for what this node depends on directly: */ #define DT_N_S_buttons_S_button_1_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000/gpio@842500 */ \ 14, /* /buttons */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_buttons_S_button_1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_buttons_S_button_1_EXISTS 1 #define DT_N_ALIAS_sw1 DT_N_S_buttons_S_button_1 #define DT_N_NODELABEL_button1 DT_N_S_buttons_S_button_1 /* Macros for properties that are special in the specification: */ #define DT_N_S_buttons_S_button_1_REG_NUM 0 #define DT_N_S_buttons_S_button_1_RANGES_NUM 0 #define DT_N_S_buttons_S_button_1_FOREACH_RANGE(fn) #define DT_N_S_buttons_S_button_1_IRQ_NUM 0 #define DT_N_S_buttons_S_button_1_IRQ_LEVEL 0 #define DT_N_S_buttons_S_button_1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_buttons_S_button_1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin 9 #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags 17 #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_1, gpios, 0) #define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_1, gpios, 0) #define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_1, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_1, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_1_P_gpios_LEN 1 #define DT_N_S_buttons_S_button_1_P_gpios_EXISTS 1 #define DT_N_S_buttons_S_button_1_P_label "Push button 2" #define DT_N_S_buttons_S_button_1_P_label_STRING_UNQUOTED Push button 2 #define DT_N_S_buttons_S_button_1_P_label_STRING_TOKEN Push_button_2 #define DT_N_S_buttons_S_button_1_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_2 #define DT_N_S_buttons_S_button_1_P_label_IDX_0 "Push button 2" #define DT_N_S_buttons_S_button_1_P_label_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_1, label, 0) #define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_1, label, 0) #define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_1, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_1, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_1_P_label_LEN 1 #define DT_N_S_buttons_S_button_1_P_label_EXISTS 1 #define DT_N_S_buttons_S_button_1_P_zephyr_code 2 #define DT_N_S_buttons_S_button_1_P_zephyr_code_EXISTS 1 /* * Devicetree node: /buttons/button_2 * * Node identifier: DT_N_S_buttons_S_button_2 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_buttons_S_button_2_PATH "/buttons/button_2" /* Node's name with unit-address: */ #define DT_N_S_buttons_S_button_2_FULL_NAME "button_2" /* Node parent (/buttons) identifier: */ #define DT_N_S_buttons_S_button_2_PARENT DT_N_S_buttons /* Node's index in its parent's list of children: */ #define DT_N_S_buttons_S_button_2_CHILD_IDX 2 /* Helper macros for child nodes of this node. */ #define DT_N_S_buttons_S_button_2_CHILD_NUM 0 #define DT_N_S_buttons_S_button_2_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_buttons_S_button_2_FOREACH_CHILD(fn) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_buttons_S_button_2_ORD 17 #define DT_N_S_buttons_S_button_2_ORD_STR_SORTABLE 00017 /* Ordinals for what this node depends on directly: */ #define DT_N_S_buttons_S_button_2_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000/gpio@842500 */ \ 14, /* /buttons */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_buttons_S_button_2_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_buttons_S_button_2_EXISTS 1 #define DT_N_ALIAS_sw2 DT_N_S_buttons_S_button_2 #define DT_N_NODELABEL_button2 DT_N_S_buttons_S_button_2 /* Macros for properties that are special in the specification: */ #define DT_N_S_buttons_S_button_2_REG_NUM 0 #define DT_N_S_buttons_S_button_2_RANGES_NUM 0 #define DT_N_S_buttons_S_button_2_FOREACH_RANGE(fn) #define DT_N_S_buttons_S_button_2_IRQ_NUM 0 #define DT_N_S_buttons_S_button_2_IRQ_LEVEL 0 #define DT_N_S_buttons_S_button_2_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_buttons_S_button_2_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin 18 #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags 17 #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_2, gpios, 0) #define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_2, gpios, 0) #define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_2, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_2, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_2_P_gpios_LEN 1 #define DT_N_S_buttons_S_button_2_P_gpios_EXISTS 1 #define DT_N_S_buttons_S_button_2_P_label "Push button 3" #define DT_N_S_buttons_S_button_2_P_label_STRING_UNQUOTED Push button 3 #define DT_N_S_buttons_S_button_2_P_label_STRING_TOKEN Push_button_3 #define DT_N_S_buttons_S_button_2_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_3 #define DT_N_S_buttons_S_button_2_P_label_IDX_0 "Push button 3" #define DT_N_S_buttons_S_button_2_P_label_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_2, label, 0) #define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_2, label, 0) #define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_2, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_2, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_2_P_label_LEN 1 #define DT_N_S_buttons_S_button_2_P_label_EXISTS 1 #define DT_N_S_buttons_S_button_2_P_zephyr_code 3 #define DT_N_S_buttons_S_button_2_P_zephyr_code_EXISTS 1 /* * Devicetree node: /buttons/button_3 * * Node identifier: DT_N_S_buttons_S_button_3 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_buttons_S_button_3_PATH "/buttons/button_3" /* Node's name with unit-address: */ #define DT_N_S_buttons_S_button_3_FULL_NAME "button_3" /* Node parent (/buttons) identifier: */ #define DT_N_S_buttons_S_button_3_PARENT DT_N_S_buttons /* Node's index in its parent's list of children: */ #define DT_N_S_buttons_S_button_3_CHILD_IDX 3 /* Helper macros for child nodes of this node. */ #define DT_N_S_buttons_S_button_3_CHILD_NUM 0 #define DT_N_S_buttons_S_button_3_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_buttons_S_button_3_FOREACH_CHILD(fn) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_buttons_S_button_3_ORD 18 #define DT_N_S_buttons_S_button_3_ORD_STR_SORTABLE 00018 /* Ordinals for what this node depends on directly: */ #define DT_N_S_buttons_S_button_3_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000/gpio@842500 */ \ 14, /* /buttons */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_buttons_S_button_3_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_buttons_S_button_3_EXISTS 1 #define DT_N_ALIAS_sw3 DT_N_S_buttons_S_button_3 #define DT_N_NODELABEL_button3 DT_N_S_buttons_S_button_3 /* Macros for properties that are special in the specification: */ #define DT_N_S_buttons_S_button_3_REG_NUM 0 #define DT_N_S_buttons_S_button_3_RANGES_NUM 0 #define DT_N_S_buttons_S_button_3_FOREACH_RANGE(fn) #define DT_N_S_buttons_S_button_3_IRQ_NUM 0 #define DT_N_S_buttons_S_button_3_IRQ_LEVEL 0 #define DT_N_S_buttons_S_button_3_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_buttons_S_button_3_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin 19 #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags 17 #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_3, gpios, 0) #define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_3, gpios, 0) #define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_3, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_3, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_3_P_gpios_LEN 1 #define DT_N_S_buttons_S_button_3_P_gpios_EXISTS 1 #define DT_N_S_buttons_S_button_3_P_label "Push button 4" #define DT_N_S_buttons_S_button_3_P_label_STRING_UNQUOTED Push button 4 #define DT_N_S_buttons_S_button_3_P_label_STRING_TOKEN Push_button_4 #define DT_N_S_buttons_S_button_3_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_4 #define DT_N_S_buttons_S_button_3_P_label_IDX_0 "Push button 4" #define DT_N_S_buttons_S_button_3_P_label_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_3, label, 0) #define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_3, label, 0) #define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_3, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_3, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_3_P_label_LEN 1 #define DT_N_S_buttons_S_button_3_P_label_EXISTS 1 #define DT_N_S_buttons_S_button_3_P_zephyr_code 4 #define DT_N_S_buttons_S_button_3_P_zephyr_code_EXISTS 1 /* * Devicetree node: /cpus * * Node identifier: DT_N_S_cpus */ /* Node's full path: */ #define DT_N_S_cpus_PATH "/cpus" /* Node's name with unit-address: */ #define DT_N_S_cpus_FULL_NAME "cpus" /* Node parent (/) identifier: */ #define DT_N_S_cpus_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_cpus_CHILD_IDX 6 /* Helper macros for child nodes of this node. */ #define DT_N_S_cpus_CHILD_NUM 1 #define DT_N_S_cpus_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0) #define DT_N_S_cpus_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0) #define DT_N_S_cpus_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) #define DT_N_S_cpus_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0) #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0) #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_cpus_ORD 19 #define DT_N_S_cpus_ORD_STR_SORTABLE 00019 /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_SUPPORTS_ORDS \ 20, /* /cpus/cpu@0 */ /* Existence and alternate IDs: */ #define DT_N_S_cpus_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_cpus_REG_NUM 0 #define DT_N_S_cpus_RANGES_NUM 0 #define DT_N_S_cpus_FOREACH_RANGE(fn) #define DT_N_S_cpus_IRQ_NUM 0 #define DT_N_S_cpus_IRQ_LEVEL 0 #define DT_N_S_cpus_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_cpus_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /cpus/cpu@0 * * Node identifier: DT_N_S_cpus_S_cpu_0 * * Binding (compatible = arm,cortex-m33f): * $ZEPHYR_BASE/dts/bindings/cpu/arm,cortex-m33f.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_cpus_S_cpu_0_PATH "/cpus/cpu@0" /* Node's name with unit-address: */ #define DT_N_S_cpus_S_cpu_0_FULL_NAME "cpu@0" /* Node parent (/cpus) identifier: */ #define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus /* Node's index in its parent's list of children: */ #define DT_N_S_cpus_S_cpu_0_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_cpus_S_cpu_0_CHILD_NUM 1 #define DT_N_S_cpus_S_cpu_0_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_cpus_S_cpu_0_ORD 20 #define DT_N_S_cpus_S_cpu_0_ORD_STR_SORTABLE 00020 /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \ 19, /* /cpus */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS \ 21, /* /cpus/cpu@0/mpu@e000ed90 */ /* Existence and alternate IDs: */ #define DT_N_S_cpus_S_cpu_0_EXISTS 1 #define DT_N_INST_0_arm_cortex_m33f DT_N_S_cpus_S_cpu_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_cpus_S_cpu_0_REG_NUM 1 #define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ #define DT_N_S_cpus_S_cpu_0_RANGES_NUM 0 #define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn) #define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0 #define DT_N_S_cpus_S_cpu_0_IRQ_LEVEL 0 #define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m33f 1 #define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0 "ARM Ltd." #define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0 "cortex-m33f" #define DT_N_S_cpus_S_cpu_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_cpus_S_cpu_0_P_wakeup_source 0 #define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_compatible {"arm,cortex-m33f"} #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "arm,cortex-m33f" #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UNQUOTED arm,cortex-m33f #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_TOKEN arm_cortex_m33f #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_CORTEX_M33F #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, compatible, 0) #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, compatible, 0) #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1 #define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */} #define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0 #define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init 0 #define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /cpus/cpu@0/mpu@e000ed90 * * Node identifier: DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90 * * Binding (compatible = arm,armv8m-mpu): * $ZEPHYR_BASE/dts/bindings/mmu_mpu/arm,armv8m-mpu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PATH "/cpus/cpu@0/mpu@e000ed90" /* Node's name with unit-address: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME "mpu@e000ed90" /* Node parent (/cpus/cpu@0) identifier: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PARENT DT_N_S_cpus_S_cpu_0 /* Node's index in its parent's list of children: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_NUM 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD(fn) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD 21 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD_STR_SORTABLE 00021 /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REQUIRES_ORDS \ 20, /* /cpus/cpu@0 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_EXISTS 1 #define DT_N_INST_0_arm_armv8m_mpu DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90 #define DT_N_NODELABEL_mpu DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90 /* Macros for properties that are special in the specification: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_NUM 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS 3758157200 /* 0xe000ed90 */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE 64 /* 0x40 */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_RANGES_NUM 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_RANGE(fn) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_NUM 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_LEVEL 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MATCHES_arm_armv8m_mpu 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_VENDOR_IDX_0 "ARM Ltd." #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MODEL_IDX_0 "armv8m-mpu" #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible {"arm,armv8m-mpu"} #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0 "arm,armv8m-mpu" #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-mpu #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_mpu #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_MPU #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_LEN 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg {3758157200 /* 0xe000ed90 */, 64 /* 0x40 */} #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0 3758157200 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1 64 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_deferred_init 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /leds * * Node identifier: DT_N_S_leds * * Binding (compatible = gpio-leds): * $ZEPHYR_BASE/dts/bindings/led/gpio-leds.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_leds_PATH "/leds" /* Node's name with unit-address: */ #define DT_N_S_leds_FULL_NAME "leds" /* Node parent (/) identifier: */ #define DT_N_S_leds_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_leds_CHILD_IDX 7 /* Helper macros for child nodes of this node. */ #define DT_N_S_leds_CHILD_NUM 4 #define DT_N_S_leds_CHILD_NUM_STATUS_OKAY 4 #define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) #define DT_N_S_leds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_leds_S_led_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3) #define DT_N_S_leds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) #define DT_N_S_leds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3, __VA_ARGS__) #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_leds_S_led_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3) #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_leds_ORD 22 #define DT_N_S_leds_ORD_STR_SORTABLE 00022 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_REQUIRES_ORDS \ 0, /* / */ \ 10, /* /soc/peripheral@50000000/gpio@842500 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_SUPPORTS_ORDS \ 23, /* /leds/led_0 */ \ 24, /* /leds/led_1 */ \ 25, /* /leds/led_2 */ \ 26, /* /leds/led_3 */ /* Existence and alternate IDs: */ #define DT_N_S_leds_EXISTS 1 #define DT_N_INST_0_gpio_leds DT_N_S_leds /* Macros for properties that are special in the specification: */ #define DT_N_S_leds_REG_NUM 0 #define DT_N_S_leds_RANGES_NUM 0 #define DT_N_S_leds_FOREACH_RANGE(fn) #define DT_N_S_leds_IRQ_NUM 0 #define DT_N_S_leds_IRQ_LEVEL 0 #define DT_N_S_leds_COMPAT_MATCHES_gpio_leds 1 #define DT_N_S_leds_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_leds_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_leds_P_compatible {"gpio-leds"} #define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds" #define DT_N_S_leds_P_compatible_IDX_0_STRING_UNQUOTED gpio-leds #define DT_N_S_leds_P_compatible_IDX_0_STRING_TOKEN gpio_leds #define DT_N_S_leds_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_LEDS #define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds, compatible, 0) #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds, compatible, 0) #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__) #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__) #define DT_N_S_leds_P_compatible_LEN 1 #define DT_N_S_leds_P_compatible_EXISTS 1 /* * Devicetree node: /leds/led_0 * * Node identifier: DT_N_S_leds_S_led_0 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_leds_S_led_0_PATH "/leds/led_0" /* Node's name with unit-address: */ #define DT_N_S_leds_S_led_0_FULL_NAME "led_0" /* Node parent (/leds) identifier: */ #define DT_N_S_leds_S_led_0_PARENT DT_N_S_leds /* Node's index in its parent's list of children: */ #define DT_N_S_leds_S_led_0_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_leds_S_led_0_CHILD_NUM 0 #define DT_N_S_leds_S_led_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_leds_S_led_0_FOREACH_CHILD(fn) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_leds_S_led_0_ORD 23 #define DT_N_S_leds_S_led_0_ORD_STR_SORTABLE 00023 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_0_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000/gpio@842500 */ \ 22, /* /leds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_leds_S_led_0_EXISTS 1 #define DT_N_ALIAS_led0 DT_N_S_leds_S_led_0 #define DT_N_ALIAS_bootloader_led0 DT_N_S_leds_S_led_0 #define DT_N_ALIAS_mcuboot_led0 DT_N_S_leds_S_led_0 #define DT_N_NODELABEL_led0 DT_N_S_leds_S_led_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_leds_S_led_0_REG_NUM 0 #define DT_N_S_leds_S_led_0_RANGES_NUM 0 #define DT_N_S_leds_S_led_0_FOREACH_RANGE(fn) #define DT_N_S_leds_S_led_0_IRQ_NUM 0 #define DT_N_S_leds_S_led_0_IRQ_LEVEL 0 #define DT_N_S_leds_S_led_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_leds_S_led_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin 0 #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags 0 #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, gpios, 0) #define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, gpios, 0) #define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_0_P_gpios_LEN 1 #define DT_N_S_leds_S_led_0_P_gpios_EXISTS 1 #define DT_N_S_leds_S_led_0_P_label "Green LED 1" #define DT_N_S_leds_S_led_0_P_label_STRING_UNQUOTED Green LED 1 #define DT_N_S_leds_S_led_0_P_label_STRING_TOKEN Green_LED_1 #define DT_N_S_leds_S_led_0_P_label_STRING_UPPER_TOKEN GREEN_LED_1 #define DT_N_S_leds_S_led_0_P_label_IDX_0 "Green LED 1" #define DT_N_S_leds_S_led_0_P_label_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, label, 0) #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, label, 0) #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_0_P_label_LEN 1 #define DT_N_S_leds_S_led_0_P_label_EXISTS 1 /* * Devicetree node: /leds/led_1 * * Node identifier: DT_N_S_leds_S_led_1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_leds_S_led_1_PATH "/leds/led_1" /* Node's name with unit-address: */ #define DT_N_S_leds_S_led_1_FULL_NAME "led_1" /* Node parent (/leds) identifier: */ #define DT_N_S_leds_S_led_1_PARENT DT_N_S_leds /* Node's index in its parent's list of children: */ #define DT_N_S_leds_S_led_1_CHILD_IDX 1 /* Helper macros for child nodes of this node. */ #define DT_N_S_leds_S_led_1_CHILD_NUM 0 #define DT_N_S_leds_S_led_1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_leds_S_led_1_FOREACH_CHILD(fn) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_leds_S_led_1_ORD 24 #define DT_N_S_leds_S_led_1_ORD_STR_SORTABLE 00024 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_1_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000/gpio@842500 */ \ 22, /* /leds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_leds_S_led_1_EXISTS 1 #define DT_N_ALIAS_led1 DT_N_S_leds_S_led_1 #define DT_N_NODELABEL_led1 DT_N_S_leds_S_led_1 /* Macros for properties that are special in the specification: */ #define DT_N_S_leds_S_led_1_REG_NUM 0 #define DT_N_S_leds_S_led_1_RANGES_NUM 0 #define DT_N_S_leds_S_led_1_FOREACH_RANGE(fn) #define DT_N_S_leds_S_led_1_IRQ_NUM 0 #define DT_N_S_leds_S_led_1_IRQ_LEVEL 0 #define DT_N_S_leds_S_led_1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_leds_S_led_1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin 1 #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags 0 #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, gpios, 0) #define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, gpios, 0) #define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_1_P_gpios_LEN 1 #define DT_N_S_leds_S_led_1_P_gpios_EXISTS 1 #define DT_N_S_leds_S_led_1_P_label "Green LED 2" #define DT_N_S_leds_S_led_1_P_label_STRING_UNQUOTED Green LED 2 #define DT_N_S_leds_S_led_1_P_label_STRING_TOKEN Green_LED_2 #define DT_N_S_leds_S_led_1_P_label_STRING_UPPER_TOKEN GREEN_LED_2 #define DT_N_S_leds_S_led_1_P_label_IDX_0 "Green LED 2" #define DT_N_S_leds_S_led_1_P_label_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, label, 0) #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, label, 0) #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_1_P_label_LEN 1 #define DT_N_S_leds_S_led_1_P_label_EXISTS 1 /* * Devicetree node: /leds/led_2 * * Node identifier: DT_N_S_leds_S_led_2 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_leds_S_led_2_PATH "/leds/led_2" /* Node's name with unit-address: */ #define DT_N_S_leds_S_led_2_FULL_NAME "led_2" /* Node parent (/leds) identifier: */ #define DT_N_S_leds_S_led_2_PARENT DT_N_S_leds /* Node's index in its parent's list of children: */ #define DT_N_S_leds_S_led_2_CHILD_IDX 2 /* Helper macros for child nodes of this node. */ #define DT_N_S_leds_S_led_2_CHILD_NUM 0 #define DT_N_S_leds_S_led_2_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_leds_S_led_2_FOREACH_CHILD(fn) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_leds_S_led_2_ORD 25 #define DT_N_S_leds_S_led_2_ORD_STR_SORTABLE 00025 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_2_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000/gpio@842500 */ \ 22, /* /leds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_2_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_leds_S_led_2_EXISTS 1 #define DT_N_ALIAS_led2 DT_N_S_leds_S_led_2 #define DT_N_NODELABEL_led2 DT_N_S_leds_S_led_2 /* Macros for properties that are special in the specification: */ #define DT_N_S_leds_S_led_2_REG_NUM 0 #define DT_N_S_leds_S_led_2_RANGES_NUM 0 #define DT_N_S_leds_S_led_2_FOREACH_RANGE(fn) #define DT_N_S_leds_S_led_2_IRQ_NUM 0 #define DT_N_S_leds_S_led_2_IRQ_LEVEL 0 #define DT_N_S_leds_S_led_2_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_leds_S_led_2_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin 4 #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags 0 #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, gpios, 0) #define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, gpios, 0) #define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_2_P_gpios_LEN 1 #define DT_N_S_leds_S_led_2_P_gpios_EXISTS 1 #define DT_N_S_leds_S_led_2_P_label "Green LED 3" #define DT_N_S_leds_S_led_2_P_label_STRING_UNQUOTED Green LED 3 #define DT_N_S_leds_S_led_2_P_label_STRING_TOKEN Green_LED_3 #define DT_N_S_leds_S_led_2_P_label_STRING_UPPER_TOKEN GREEN_LED_3 #define DT_N_S_leds_S_led_2_P_label_IDX_0 "Green LED 3" #define DT_N_S_leds_S_led_2_P_label_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, label, 0) #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, label, 0) #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_2_P_label_LEN 1 #define DT_N_S_leds_S_led_2_P_label_EXISTS 1 /* * Devicetree node: /leds/led_3 * * Node identifier: DT_N_S_leds_S_led_3 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_leds_S_led_3_PATH "/leds/led_3" /* Node's name with unit-address: */ #define DT_N_S_leds_S_led_3_FULL_NAME "led_3" /* Node parent (/leds) identifier: */ #define DT_N_S_leds_S_led_3_PARENT DT_N_S_leds /* Node's index in its parent's list of children: */ #define DT_N_S_leds_S_led_3_CHILD_IDX 3 /* Helper macros for child nodes of this node. */ #define DT_N_S_leds_S_led_3_CHILD_NUM 0 #define DT_N_S_leds_S_led_3_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_leds_S_led_3_FOREACH_CHILD(fn) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_leds_S_led_3_ORD 26 #define DT_N_S_leds_S_led_3_ORD_STR_SORTABLE 00026 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_3_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000/gpio@842500 */ \ 22, /* /leds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_3_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_leds_S_led_3_EXISTS 1 #define DT_N_ALIAS_led3 DT_N_S_leds_S_led_3 #define DT_N_NODELABEL_led3 DT_N_S_leds_S_led_3 /* Macros for properties that are special in the specification: */ #define DT_N_S_leds_S_led_3_REG_NUM 0 #define DT_N_S_leds_S_led_3_RANGES_NUM 0 #define DT_N_S_leds_S_led_3_FOREACH_RANGE(fn) #define DT_N_S_leds_S_led_3_IRQ_NUM 0 #define DT_N_S_leds_S_led_3_IRQ_LEVEL 0 #define DT_N_S_leds_S_led_3_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_leds_S_led_3_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin 5 #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags 0 #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_3, gpios, 0) #define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, gpios, 0) #define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_3, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_3, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_3_P_gpios_LEN 1 #define DT_N_S_leds_S_led_3_P_gpios_EXISTS 1 #define DT_N_S_leds_S_led_3_P_label "Green LED 4" #define DT_N_S_leds_S_led_3_P_label_STRING_UNQUOTED Green LED 4 #define DT_N_S_leds_S_led_3_P_label_STRING_TOKEN Green_LED_4 #define DT_N_S_leds_S_led_3_P_label_STRING_UPPER_TOKEN GREEN_LED_4 #define DT_N_S_leds_S_led_3_P_label_IDX_0 "Green LED 4" #define DT_N_S_leds_S_led_3_P_label_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_3, label, 0) #define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, label, 0) #define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_3, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_3, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_3_P_label_LEN 1 #define DT_N_S_leds_S_led_3_P_label_EXISTS 1 /* * Devicetree node: /pin-controller * * Node identifier: DT_N_S_pin_controller * * Binding (compatible = nordic,nrf-pinctrl): * $ZEPHYR_BASE/dts/bindings/pinctrl/nordic,nrf-pinctrl.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_PATH "/pin-controller" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_FULL_NAME "pin-controller" /* Node parent (/) identifier: */ #define DT_N_S_pin_controller_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_CHILD_IDX 3 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_CHILD_NUM 10 #define DT_N_S_pin_controller_CHILD_NUM_STATUS_OKAY 10 #define DT_N_S_pin_controller_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_i2c2_default) fn(DT_N_S_pin_controller_S_i2c2_sleep) fn(DT_N_S_pin_controller_S_pwm0_default) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_spi3_default) fn(DT_N_S_pin_controller_S_spi3_sleep) #define DT_N_S_pin_controller_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_sleep) #define DT_N_S_pin_controller_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_i2c2_default) fn(DT_N_S_pin_controller_S_i2c2_sleep) fn(DT_N_S_pin_controller_S_pwm0_default) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_spi3_default) fn(DT_N_S_pin_controller_S_spi3_sleep) #define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_sleep) #define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_ORD 27 #define DT_N_S_pin_controller_ORD_STR_SORTABLE 00027 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_SUPPORTS_ORDS \ 28, /* /pin-controller/i2c2_default */ \ 30, /* /pin-controller/i2c2_sleep */ \ 32, /* /pin-controller/pwm0_default */ \ 34, /* /pin-controller/pwm0_sleep */ \ 36, /* /pin-controller/spi3_default */ \ 38, /* /pin-controller/spi3_sleep */ \ 40, /* /pin-controller/uart0_default */ \ 43, /* /pin-controller/uart0_sleep */ \ 45, /* /pin-controller/uart1_default */ \ 48, /* /pin-controller/uart1_sleep */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_EXISTS 1 #define DT_N_INST_0_nordic_nrf_pinctrl DT_N_S_pin_controller #define DT_N_NODELABEL_pinctrl DT_N_S_pin_controller /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_REG_NUM 0 #define DT_N_S_pin_controller_RANGES_NUM 0 #define DT_N_S_pin_controller_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_IRQ_NUM 0 #define DT_N_S_pin_controller_IRQ_LEVEL 0 #define DT_N_S_pin_controller_COMPAT_MATCHES_nordic_nrf_pinctrl 1 #define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0 "nrf-pinctrl" #define DT_N_S_pin_controller_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_P_wakeup_source 0 #define DT_N_S_pin_controller_P_wakeup_source_EXISTS 1 #define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_pin_controller_P_compatible {"nordic,nrf-pinctrl"} #define DT_N_S_pin_controller_P_compatible_IDX_0 "nordic,nrf-pinctrl" #define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pinctrl #define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pinctrl #define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PINCTRL #define DT_N_S_pin_controller_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller, compatible, 0) #define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller, compatible, 0) #define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__) #define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__) #define DT_N_S_pin_controller_P_compatible_LEN 1 #define DT_N_S_pin_controller_P_compatible_EXISTS 1 #define DT_N_S_pin_controller_P_zephyr_deferred_init 0 #define DT_N_S_pin_controller_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /pin-controller/i2c2_default * * Node identifier: DT_N_S_pin_controller_S_i2c2_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_i2c2_default_PATH "/pin-controller/i2c2_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_i2c2_default_FULL_NAME "i2c2_default" /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_i2c2_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_i2c2_default_CHILD_IDX 4 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_i2c2_default_CHILD_NUM 1 #define DT_N_S_pin_controller_S_i2c2_default_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1) #define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1) #define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1) #define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1) #define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_i2c2_default_ORD 28 #define DT_N_S_pin_controller_S_i2c2_default_ORD_STR_SORTABLE 00028 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_i2c2_default_REQUIRES_ORDS \ 27, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_i2c2_default_SUPPORTS_ORDS \ 29, /* /pin-controller/i2c2_default/group1 */ \ 107, /* /soc/peripheral@50000000/i2c@a000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_i2c2_default_EXISTS 1 #define DT_N_NODELABEL_i2c2_default DT_N_S_pin_controller_S_i2c2_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_i2c2_default_REG_NUM 0 #define DT_N_S_pin_controller_S_i2c2_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_i2c2_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_i2c2_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_i2c2_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_i2c2_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_i2c2_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/i2c2_default/group1 * * Node identifier: DT_N_S_pin_controller_S_i2c2_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_i2c2_default_S_group1_PATH "/pin-controller/i2c2_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_i2c2_default_S_group1_FULL_NAME "group1" /* Node parent (/pin-controller/i2c2_default) identifier: */ #define DT_N_S_pin_controller_S_i2c2_default_S_group1_PARENT DT_N_S_pin_controller_S_i2c2_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_i2c2_default_S_group1_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_i2c2_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_i2c2_default_S_group1_ORD 29 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_ORD_STR_SORTABLE 00029 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_i2c2_default_S_group1_REQUIRES_ORDS \ 28, /* /pin-controller/i2c2_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_i2c2_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_i2c2_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_i2c2_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_i2c2_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_i2c2_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_low_power_enable_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels {1572894 /* 0x18001e */, 1441823 /* 0x16001f */} #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_IDX_0 1572894 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_IDX_1 1441823 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_LEN 2 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_nordic_invert_EXISTS 1 /* * Devicetree node: /pin-controller/i2c2_sleep * * Node identifier: DT_N_S_pin_controller_S_i2c2_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_i2c2_sleep_PATH "/pin-controller/i2c2_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_i2c2_sleep_FULL_NAME "i2c2_sleep" /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_i2c2_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_i2c2_sleep_CHILD_IDX 5 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_i2c2_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_i2c2_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1) #define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1) #define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1) #define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1) #define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_i2c2_sleep_ORD 30 #define DT_N_S_pin_controller_S_i2c2_sleep_ORD_STR_SORTABLE 00030 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_i2c2_sleep_REQUIRES_ORDS \ 27, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_i2c2_sleep_SUPPORTS_ORDS \ 31, /* /pin-controller/i2c2_sleep/group1 */ \ 107, /* /soc/peripheral@50000000/i2c@a000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_i2c2_sleep_EXISTS 1 #define DT_N_NODELABEL_i2c2_sleep DT_N_S_pin_controller_S_i2c2_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_i2c2_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_i2c2_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_i2c2_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_i2c2_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_i2c2_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_i2c2_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/i2c2_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_i2c2_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_PATH "/pin-controller/i2c2_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FULL_NAME "group1" /* Node parent (/pin-controller/i2c2_sleep) identifier: */ #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_PARENT DT_N_S_pin_controller_S_i2c2_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_ORD 31 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_ORD_STR_SORTABLE 00031 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_REQUIRES_ORDS \ 30, /* /pin-controller/i2c2_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_low_power_enable_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels {1572894 /* 0x18001e */, 1441823 /* 0x16001f */} #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_IDX_0 1572894 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_IDX_1 1441823 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 1) #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 1) #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_LEN 2 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_nordic_invert_EXISTS 1 /* * Devicetree node: /pin-controller/pwm0_default * * Node identifier: DT_N_S_pin_controller_S_pwm0_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm0_default_PATH "/pin-controller/pwm0_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm0_default_FULL_NAME "pwm0_default" /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_pwm0_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm0_default_CHILD_IDX 6 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm0_default_CHILD_NUM 1 #define DT_N_S_pin_controller_S_pwm0_default_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1) #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1) #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1) #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1) #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm0_default_ORD 32 #define DT_N_S_pin_controller_S_pwm0_default_ORD_STR_SORTABLE 00032 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm0_default_REQUIRES_ORDS \ 27, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm0_default_SUPPORTS_ORDS \ 33, /* /pin-controller/pwm0_default/group1 */ \ 50, /* /soc/peripheral@50000000/pwm@21000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm0_default_EXISTS 1 #define DT_N_NODELABEL_pwm0_default DT_N_S_pin_controller_S_pwm0_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm0_default_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm0_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm0_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm0_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm0_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm0_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/pwm0_default/group1 * * Node identifier: DT_N_S_pin_controller_S_pwm0_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm0_default_S_group1_PATH "/pin-controller/pwm0_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FULL_NAME "group1" /* Node parent (/pin-controller/pwm0_default) identifier: */ #define DT_N_S_pin_controller_S_pwm0_default_S_group1_PARENT DT_N_S_pin_controller_S_pwm0_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm0_default_S_group1_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm0_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm0_default_S_group1_ORD 33 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_ORD_STR_SORTABLE 00033 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm0_default_S_group1_REQUIRES_ORDS \ 32, /* /pin-controller/pwm0_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm0_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm0_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm0_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm0_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm0_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_low_power_enable_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels {2883584 /* 0x2c0000 */} #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_IDX_0 2883584 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_LEN 1 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_nordic_invert_EXISTS 1 /* * Devicetree node: /pin-controller/pwm0_sleep * * Node identifier: DT_N_S_pin_controller_S_pwm0_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm0_sleep_PATH "/pin-controller/pwm0_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm0_sleep_FULL_NAME "pwm0_sleep" /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_pwm0_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm0_sleep_CHILD_IDX 7 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm0_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_pwm0_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm0_sleep_ORD 34 #define DT_N_S_pin_controller_S_pwm0_sleep_ORD_STR_SORTABLE 00034 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm0_sleep_REQUIRES_ORDS \ 27, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm0_sleep_SUPPORTS_ORDS \ 35, /* /pin-controller/pwm0_sleep/group1 */ \ 50, /* /soc/peripheral@50000000/pwm@21000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm0_sleep_EXISTS 1 #define DT_N_NODELABEL_pwm0_sleep DT_N_S_pin_controller_S_pwm0_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm0_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm0_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm0_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm0_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/pwm0_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_pwm0_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_PATH "/pin-controller/pwm0_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FULL_NAME "group1" /* Node parent (/pin-controller/pwm0_sleep) identifier: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_PARENT DT_N_S_pin_controller_S_pwm0_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_ORD 35 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_ORD_STR_SORTABLE 00035 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_REQUIRES_ORDS \ 34, /* /pin-controller/pwm0_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_low_power_enable_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels {2883584 /* 0x2c0000 */} #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_IDX_0 2883584 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_LEN 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_invert_EXISTS 1 /* * Devicetree node: /pin-controller/spi3_default * * Node identifier: DT_N_S_pin_controller_S_spi3_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi3_default_PATH "/pin-controller/spi3_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi3_default_FULL_NAME "spi3_default" /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_spi3_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi3_default_CHILD_IDX 8 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi3_default_CHILD_NUM 1 #define DT_N_S_pin_controller_S_spi3_default_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi3_default_S_group1) #define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_default_S_group1) #define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi3_default_S_group1) #define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_default_S_group1) #define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi3_default_ORD 36 #define DT_N_S_pin_controller_S_spi3_default_ORD_STR_SORTABLE 00036 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi3_default_REQUIRES_ORDS \ 27, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi3_default_SUPPORTS_ORDS \ 37, /* /pin-controller/spi3_default/group1 */ \ 112, /* /soc/peripheral@50000000/spi@b000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi3_default_EXISTS 1 #define DT_N_NODELABEL_spi3_default DT_N_S_pin_controller_S_spi3_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi3_default_REG_NUM 0 #define DT_N_S_pin_controller_S_spi3_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi3_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi3_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi3_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi3_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi3_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/spi3_default/group1 * * Node identifier: DT_N_S_pin_controller_S_spi3_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi3_default_S_group1_PATH "/pin-controller/spi3_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi3_default_S_group1_FULL_NAME "group1" /* Node parent (/pin-controller/spi3_default) identifier: */ #define DT_N_S_pin_controller_S_spi3_default_S_group1_PARENT DT_N_S_pin_controller_S_spi3_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi3_default_S_group1_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi3_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_spi3_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi3_default_S_group1_ORD 37 #define DT_N_S_pin_controller_S_spi3_default_S_group1_ORD_STR_SORTABLE 00037 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi3_default_S_group1_REQUIRES_ORDS \ 36, /* /pin-controller/spi3_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi3_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi3_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi3_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_spi3_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi3_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi3_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi3_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi3_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_low_power_enable_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels {524301 /* 0x8000d */, 786444 /* 0xc000c */, 655371 /* 0xa000b */} #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_0 524301 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_1 786444 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_2 655371 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_LEN 3 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_nordic_drive_mode 3 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_spi3_default_S_group1_P_nordic_invert_EXISTS 1 /* * Devicetree node: /pin-controller/spi3_sleep * * Node identifier: DT_N_S_pin_controller_S_spi3_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi3_sleep_PATH "/pin-controller/spi3_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi3_sleep_FULL_NAME "spi3_sleep" /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_spi3_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi3_sleep_CHILD_IDX 9 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi3_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_spi3_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1) #define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1) #define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1) #define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1) #define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi3_sleep_ORD 38 #define DT_N_S_pin_controller_S_spi3_sleep_ORD_STR_SORTABLE 00038 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi3_sleep_REQUIRES_ORDS \ 27, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi3_sleep_SUPPORTS_ORDS \ 39, /* /pin-controller/spi3_sleep/group1 */ \ 112, /* /soc/peripheral@50000000/spi@b000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi3_sleep_EXISTS 1 #define DT_N_NODELABEL_spi3_sleep DT_N_S_pin_controller_S_spi3_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi3_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_spi3_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi3_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi3_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi3_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi3_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/spi3_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_spi3_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_PATH "/pin-controller/spi3_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FULL_NAME "group1" /* Node parent (/pin-controller/spi3_sleep) identifier: */ #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi3_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_ORD 39 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_ORD_STR_SORTABLE 00039 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_REQUIRES_ORDS \ 38, /* /pin-controller/spi3_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_low_power_enable_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels {524301 /* 0x8000d */, 786444 /* 0xc000c */, 655371 /* 0xa000b */} #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_0 524301 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_1 786444 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_2 655371 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_LEN 3 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_nordic_invert_EXISTS 1 /* * Devicetree node: /pin-controller/uart0_default * * Node identifier: DT_N_S_pin_controller_S_uart0_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart0_default_PATH "/pin-controller/uart0_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart0_default_FULL_NAME "uart0_default" /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_uart0_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart0_default_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart0_default_CHILD_NUM 2 #define DT_N_S_pin_controller_S_uart0_default_CHILD_NUM_STATUS_OKAY 2 #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart0_default_ORD 40 #define DT_N_S_pin_controller_S_uart0_default_ORD_STR_SORTABLE 00040 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart0_default_REQUIRES_ORDS \ 27, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart0_default_SUPPORTS_ORDS \ 41, /* /pin-controller/uart0_default/group1 */ \ 42, /* /pin-controller/uart0_default/group2 */ \ 92, /* /soc/peripheral@50000000/uart@8000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart0_default_EXISTS 1 #define DT_N_NODELABEL_uart0_default DT_N_S_pin_controller_S_uart0_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart0_default_REG_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart0_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart0_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart0_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/uart0_default/group1 * * Node identifier: DT_N_S_pin_controller_S_uart0_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_PATH "/pin-controller/uart0_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME "group1" /* Node parent (/pin-controller/uart0_default) identifier: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_PARENT DT_N_S_pin_controller_S_uart0_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_ORD 41 #define DT_N_S_pin_controller_S_uart0_default_S_group1_ORD_STR_SORTABLE 00041 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_REQUIRES_ORDS \ 40, /* /pin-controller/uart0_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels {27 /* 0x1b */, 262158 /* 0x4000e */} #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0 27 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_1 262158 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_LEN 2 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert_EXISTS 1 /* * Devicetree node: /pin-controller/uart0_default/group2 * * Node identifier: DT_N_S_pin_controller_S_uart0_default_S_group2 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_PATH "/pin-controller/uart0_default/group2" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME "group2" /* Node parent (/pin-controller/uart0_default) identifier: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_PARENT DT_N_S_pin_controller_S_uart0_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_IDX 1 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_ORD 42 #define DT_N_S_pin_controller_S_uart0_default_S_group2_ORD_STR_SORTABLE 00042 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_REQUIRES_ORDS \ 40, /* /pin-controller/uart0_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_REG_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group2_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels {131098 /* 0x2001a */, 393231 /* 0x6000f */} #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0 131098 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_1 393231 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0) \ fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1) #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1) #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_LEN 2 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert_EXISTS 1 /* * Devicetree node: /pin-controller/uart0_sleep * * Node identifier: DT_N_S_pin_controller_S_uart0_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart0_sleep_PATH "/pin-controller/uart0_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart0_sleep_FULL_NAME "uart0_sleep" /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_uart0_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart0_sleep_CHILD_IDX 1 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart0_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_uart0_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart0_sleep_ORD 43 #define DT_N_S_pin_controller_S_uart0_sleep_ORD_STR_SORTABLE 00043 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart0_sleep_REQUIRES_ORDS \ 27, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart0_sleep_SUPPORTS_ORDS \ 44, /* /pin-controller/uart0_sleep/group1 */ \ 92, /* /soc/peripheral@50000000/uart@8000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart0_sleep_EXISTS 1 #define DT_N_NODELABEL_uart0_sleep DT_N_S_pin_controller_S_uart0_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart0_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart0_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart0_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart0_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/uart0_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_uart0_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PATH "/pin-controller/uart0_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FULL_NAME "group1" /* Node parent (/pin-controller/uart0_sleep) identifier: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PARENT DT_N_S_pin_controller_S_uart0_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_ORD 44 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_ORD_STR_SORTABLE 00044 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REQUIRES_ORDS \ 43, /* /pin-controller/uart0_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels {27 /* 0x1b */, 131098 /* 0x2001a */, 262158 /* 0x4000e */, 393231 /* 0x6000f */} #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0 27 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1 131098 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_2 262158 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_3 393231 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_3_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2) \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_LEN 4 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert_EXISTS 1 /* * Devicetree node: /pin-controller/uart1_default * * Node identifier: DT_N_S_pin_controller_S_uart1_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart1_default_PATH "/pin-controller/uart1_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart1_default_FULL_NAME "uart1_default" /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_uart1_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart1_default_CHILD_IDX 2 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart1_default_CHILD_NUM 2 #define DT_N_S_pin_controller_S_uart1_default_CHILD_NUM_STATUS_OKAY 2 #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart1_default_ORD 45 #define DT_N_S_pin_controller_S_uart1_default_ORD_STR_SORTABLE 00045 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart1_default_REQUIRES_ORDS \ 27, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart1_default_SUPPORTS_ORDS \ 46, /* /pin-controller/uart1_default/group1 */ \ 47, /* /pin-controller/uart1_default/group2 */ \ 93, /* /soc/peripheral@50000000/uart@9000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart1_default_EXISTS 1 #define DT_N_NODELABEL_uart1_default DT_N_S_pin_controller_S_uart1_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart1_default_REG_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart1_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart1_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart1_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/uart1_default/group1 * * Node identifier: DT_N_S_pin_controller_S_uart1_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_PATH "/pin-controller/uart1_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_FULL_NAME "group1" /* Node parent (/pin-controller/uart1_default) identifier: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_PARENT DT_N_S_pin_controller_S_uart1_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_ORD 46 #define DT_N_S_pin_controller_S_uart1_default_S_group1_ORD_STR_SORTABLE 00046 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_REQUIRES_ORDS \ 45, /* /pin-controller/uart1_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_low_power_enable_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels {29 /* 0x1d */, 262160 /* 0x40010 */} #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_IDX_0 29 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_IDX_1 262160 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_LEN 2 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_invert_EXISTS 1 /* * Devicetree node: /pin-controller/uart1_default/group2 * * Node identifier: DT_N_S_pin_controller_S_uart1_default_S_group2 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_PATH "/pin-controller/uart1_default/group2" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_FULL_NAME "group2" /* Node parent (/pin-controller/uart1_default) identifier: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_PARENT DT_N_S_pin_controller_S_uart1_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_CHILD_IDX 1 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_ORD 47 #define DT_N_S_pin_controller_S_uart1_default_S_group2_ORD_STR_SORTABLE 00047 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_REQUIRES_ORDS \ 45, /* /pin-controller/uart1_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_REG_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group2_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_up 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_low_power_enable 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_low_power_enable_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels {131100 /* 0x2001c */, 393233 /* 0x60011 */} #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_IDX_0 131100 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_IDX_1 393233 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0) \ fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 1) #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 1) #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_LEN 2 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_invert_EXISTS 1 /* * Devicetree node: /pin-controller/uart1_sleep * * Node identifier: DT_N_S_pin_controller_S_uart1_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart1_sleep_PATH "/pin-controller/uart1_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart1_sleep_FULL_NAME "uart1_sleep" /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_uart1_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart1_sleep_CHILD_IDX 3 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart1_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_uart1_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart1_sleep_ORD 48 #define DT_N_S_pin_controller_S_uart1_sleep_ORD_STR_SORTABLE 00048 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart1_sleep_REQUIRES_ORDS \ 27, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart1_sleep_SUPPORTS_ORDS \ 49, /* /pin-controller/uart1_sleep/group1 */ \ 93, /* /soc/peripheral@50000000/uart@9000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart1_sleep_EXISTS 1 #define DT_N_NODELABEL_uart1_sleep DT_N_S_pin_controller_S_uart1_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart1_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart1_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart1_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart1_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/uart1_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_uart1_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_PATH "/pin-controller/uart1_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FULL_NAME "group1" /* Node parent (/pin-controller/uart1_sleep) identifier: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_PARENT DT_N_S_pin_controller_S_uart1_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_ORD 49 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_ORD_STR_SORTABLE 00049 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_REQUIRES_ORDS \ 48, /* /pin-controller/uart1_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_low_power_enable_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels {29 /* 0x1d */, 131100 /* 0x2001c */, 262160 /* 0x40010 */, 393233 /* 0x60011 */} #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_0 29 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_1 131100 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_2 262160 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_3 393233 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_3_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 2) \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 3) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 3) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 2, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 3, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 3, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_LEN 4 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_invert_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/pwm@21000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_21000 * * Binding (compatible = nordic,nrf-pwm): * $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PATH "/soc/peripheral@50000000/pwm@21000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FULL_NAME "pwm@21000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_CHILD_IDX 27 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_ORD 50 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_ORD_STR_SORTABLE 00050 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ \ 32, /* /pin-controller/pwm0_default */ \ 34, /* /pin-controller/pwm0_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_SUPPORTS_ORDS \ 51, /* /pwmleds */ \ 52, /* /pwmleds/pwm_led_0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_21000 #define DT_N_NODELABEL_pwm0 DT_N_S_soc_S_peripheral_50000000_S_pwm_21000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_VAL_ADDRESS 1342312448 /* 0x50021000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_irq 33 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MATCHES_nordic_nrf_pwm 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MODEL_IDX_0 "nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_pwm0_default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_pwm0_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible {"nordic,nrf-pwm"} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0 "nordic,nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg {135168 /* 0x21000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_0 135168 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts {33 /* 0x21 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_0 33 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_pwm0_default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_pwm0_default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_pwm0_sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_pwm0_sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_center_aligned 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_center_aligned_EXISTS 1 /* * Devicetree node: /pwmleds * * Node identifier: DT_N_S_pwmleds * * Binding (compatible = pwm-leds): * $ZEPHYR_BASE/dts/bindings/led/pwm-leds.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pwmleds_PATH "/pwmleds" /* Node's name with unit-address: */ #define DT_N_S_pwmleds_FULL_NAME "pwmleds" /* Node parent (/) identifier: */ #define DT_N_S_pwmleds_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_pwmleds_CHILD_IDX 8 /* Helper macros for child nodes of this node. */ #define DT_N_S_pwmleds_CHILD_NUM 1 #define DT_N_S_pwmleds_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pwmleds_FOREACH_CHILD(fn) fn(DT_N_S_pwmleds_S_pwm_led_0) #define DT_N_S_pwmleds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_0) #define DT_N_S_pwmleds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) #define DT_N_S_pwmleds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) #define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pwmleds_S_pwm_led_0) #define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_0) #define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) #define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pwmleds_ORD 51 #define DT_N_S_pwmleds_ORD_STR_SORTABLE 00051 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pwmleds_REQUIRES_ORDS \ 0, /* / */ \ 50, /* /soc/peripheral@50000000/pwm@21000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pwmleds_SUPPORTS_ORDS \ 52, /* /pwmleds/pwm_led_0 */ /* Existence and alternate IDs: */ #define DT_N_S_pwmleds_EXISTS 1 #define DT_N_INST_0_pwm_leds DT_N_S_pwmleds /* Macros for properties that are special in the specification: */ #define DT_N_S_pwmleds_REG_NUM 0 #define DT_N_S_pwmleds_RANGES_NUM 0 #define DT_N_S_pwmleds_FOREACH_RANGE(fn) #define DT_N_S_pwmleds_IRQ_NUM 0 #define DT_N_S_pwmleds_IRQ_LEVEL 0 #define DT_N_S_pwmleds_COMPAT_MATCHES_pwm_leds 1 #define DT_N_S_pwmleds_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pwmleds_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pwmleds_P_compatible {"pwm-leds"} #define DT_N_S_pwmleds_P_compatible_IDX_0 "pwm-leds" #define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_UNQUOTED pwm-leds #define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_TOKEN pwm_leds #define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_UPPER_TOKEN PWM_LEDS #define DT_N_S_pwmleds_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds, compatible, 0) #define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds, compatible, 0) #define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds, compatible, 0, __VA_ARGS__) #define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds, compatible, 0, __VA_ARGS__) #define DT_N_S_pwmleds_P_compatible_LEN 1 #define DT_N_S_pwmleds_P_compatible_EXISTS 1 /* * Devicetree node: /pwmleds/pwm_led_0 * * Node identifier: DT_N_S_pwmleds_S_pwm_led_0 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pwmleds_S_pwm_led_0_PATH "/pwmleds/pwm_led_0" /* Node's name with unit-address: */ #define DT_N_S_pwmleds_S_pwm_led_0_FULL_NAME "pwm_led_0" /* Node parent (/pwmleds) identifier: */ #define DT_N_S_pwmleds_S_pwm_led_0_PARENT DT_N_S_pwmleds /* Node's index in its parent's list of children: */ #define DT_N_S_pwmleds_S_pwm_led_0_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_pwmleds_S_pwm_led_0_CHILD_NUM 0 #define DT_N_S_pwmleds_S_pwm_led_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD(fn) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pwmleds_S_pwm_led_0_ORD 52 #define DT_N_S_pwmleds_S_pwm_led_0_ORD_STR_SORTABLE 00052 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pwmleds_S_pwm_led_0_REQUIRES_ORDS \ 50, /* /soc/peripheral@50000000/pwm@21000 */ \ 51, /* /pwmleds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pwmleds_S_pwm_led_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pwmleds_S_pwm_led_0_EXISTS 1 #define DT_N_ALIAS_pwm_led0 DT_N_S_pwmleds_S_pwm_led_0 #define DT_N_NODELABEL_pwm_led0 DT_N_S_pwmleds_S_pwm_led_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_pwmleds_S_pwm_led_0_REG_NUM 0 #define DT_N_S_pwmleds_S_pwm_led_0_RANGES_NUM 0 #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_RANGE(fn) #define DT_N_S_pwmleds_S_pwm_led_0_IRQ_NUM 0 #define DT_N_S_pwmleds_S_pwm_led_0_IRQ_LEVEL 0 #define DT_N_S_pwmleds_S_pwm_led_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pwmleds_S_pwm_led_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_EXISTS 1 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_pwm_21000 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_channel 0 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_channel_EXISTS 1 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_period 20000000 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_period_EXISTS 1 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_flags 0 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0) #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0) #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_LEN 1 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_EXISTS 1 /* * Devicetree node: /reserved-memory * * Node identifier: DT_N_S_reserved_memory */ /* Node's full path: */ #define DT_N_S_reserved_memory_PATH "/reserved-memory" /* Node's name with unit-address: */ #define DT_N_S_reserved_memory_FULL_NAME "reserved-memory" /* Node parent (/) identifier: */ #define DT_N_S_reserved_memory_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_reserved_memory_CHILD_IDX 13 /* Helper macros for child nodes of this node. */ #define DT_N_S_reserved_memory_CHILD_NUM 3 #define DT_N_S_reserved_memory_CHILD_NUM_STATUS_OKAY 3 #define DT_N_S_reserved_memory_FOREACH_CHILD(fn) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_modem_20016000) fn(DT_N_S_reserved_memory_S_image_ns_20020000) #define DT_N_S_reserved_memory_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_s_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_modem_20016000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20020000) #define DT_N_S_reserved_memory_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__) #define DT_N_S_reserved_memory_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__) #define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_modem_20016000) fn(DT_N_S_reserved_memory_S_image_ns_20020000) #define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_s_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_modem_20016000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20020000) #define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__) #define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_reserved_memory_ORD 53 #define DT_N_S_reserved_memory_ORD_STR_SORTABLE 00053 /* Ordinals for what this node depends on directly: */ #define DT_N_S_reserved_memory_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_reserved_memory_SUPPORTS_ORDS \ 54, /* /reserved-memory/image_modem@20016000 */ \ 55, /* /reserved-memory/image_ns@20020000 */ \ 56, /* /reserved-memory/image_s@20000000 */ /* Existence and alternate IDs: */ #define DT_N_S_reserved_memory_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_reserved_memory_REG_NUM 0 #define DT_N_S_reserved_memory_RANGES_NUM 0 #define DT_N_S_reserved_memory_FOREACH_RANGE(fn) #define DT_N_S_reserved_memory_IRQ_NUM 0 #define DT_N_S_reserved_memory_IRQ_LEVEL 0 #define DT_N_S_reserved_memory_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_reserved_memory_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_reserved_memory_P_ranges_EXISTS 1 /* * Devicetree node: /reserved-memory/image_modem@20016000 * * Node identifier: DT_N_S_reserved_memory_S_image_modem_20016000 */ /* Node's full path: */ #define DT_N_S_reserved_memory_S_image_modem_20016000_PATH "/reserved-memory/image_modem@20016000" /* Node's name with unit-address: */ #define DT_N_S_reserved_memory_S_image_modem_20016000_FULL_NAME "image_modem@20016000" /* Node parent (/reserved-memory) identifier: */ #define DT_N_S_reserved_memory_S_image_modem_20016000_PARENT DT_N_S_reserved_memory /* Node's index in its parent's list of children: */ #define DT_N_S_reserved_memory_S_image_modem_20016000_CHILD_IDX 1 /* Helper macros for child nodes of this node. */ #define DT_N_S_reserved_memory_S_image_modem_20016000_CHILD_NUM 0 #define DT_N_S_reserved_memory_S_image_modem_20016000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD(fn) #define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_reserved_memory_S_image_modem_20016000_ORD 54 #define DT_N_S_reserved_memory_S_image_modem_20016000_ORD_STR_SORTABLE 00054 /* Ordinals for what this node depends on directly: */ #define DT_N_S_reserved_memory_S_image_modem_20016000_REQUIRES_ORDS \ 53, /* /reserved-memory */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_reserved_memory_S_image_modem_20016000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_reserved_memory_S_image_modem_20016000_EXISTS 1 #define DT_N_NODELABEL_sram0_modem DT_N_S_reserved_memory_S_image_modem_20016000 /* Macros for properties that are special in the specification: */ #define DT_N_S_reserved_memory_S_image_modem_20016000_REG_NUM 1 #define DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_VAL_ADDRESS 536961024 /* 0x20016000 */ #define DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_VAL_SIZE 40960 /* 0xa000 */ #define DT_N_S_reserved_memory_S_image_modem_20016000_RANGES_NUM 0 #define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_RANGE(fn) #define DT_N_S_reserved_memory_S_image_modem_20016000_IRQ_NUM 0 #define DT_N_S_reserved_memory_S_image_modem_20016000_IRQ_LEVEL 0 #define DT_N_S_reserved_memory_S_image_modem_20016000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_reserved_memory_S_image_modem_20016000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg {536961024 /* 0x20016000 */, 40960 /* 0xa000 */} #define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_0 536961024 #define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_1 40960 #define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_EXISTS 1 /* * Devicetree node: /reserved-memory/image_ns@20020000 * * Node identifier: DT_N_S_reserved_memory_S_image_ns_20020000 */ /* Node's full path: */ #define DT_N_S_reserved_memory_S_image_ns_20020000_PATH "/reserved-memory/image_ns@20020000" /* Node's name with unit-address: */ #define DT_N_S_reserved_memory_S_image_ns_20020000_FULL_NAME "image_ns@20020000" /* Node parent (/reserved-memory) identifier: */ #define DT_N_S_reserved_memory_S_image_ns_20020000_PARENT DT_N_S_reserved_memory /* Node's index in its parent's list of children: */ #define DT_N_S_reserved_memory_S_image_ns_20020000_CHILD_IDX 2 /* Helper macros for child nodes of this node. */ #define DT_N_S_reserved_memory_S_image_ns_20020000_CHILD_NUM 0 #define DT_N_S_reserved_memory_S_image_ns_20020000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD(fn) #define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_reserved_memory_S_image_ns_20020000_ORD 55 #define DT_N_S_reserved_memory_S_image_ns_20020000_ORD_STR_SORTABLE 00055 /* Ordinals for what this node depends on directly: */ #define DT_N_S_reserved_memory_S_image_ns_20020000_REQUIRES_ORDS \ 53, /* /reserved-memory */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_reserved_memory_S_image_ns_20020000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_reserved_memory_S_image_ns_20020000_EXISTS 1 #define DT_N_NODELABEL_sram0_ns DT_N_S_reserved_memory_S_image_ns_20020000 /* Macros for properties that are special in the specification: */ #define DT_N_S_reserved_memory_S_image_ns_20020000_REG_NUM 1 #define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_VAL_ADDRESS 537001984 /* 0x20020000 */ #define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_VAL_SIZE 131072 /* 0x20000 */ #define DT_N_S_reserved_memory_S_image_ns_20020000_RANGES_NUM 0 #define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_RANGE(fn) #define DT_N_S_reserved_memory_S_image_ns_20020000_IRQ_NUM 0 #define DT_N_S_reserved_memory_S_image_ns_20020000_IRQ_LEVEL 0 #define DT_N_S_reserved_memory_S_image_ns_20020000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_reserved_memory_S_image_ns_20020000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg {537001984 /* 0x20020000 */, 131072 /* 0x20000 */} #define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_0 537001984 #define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_1 131072 #define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_EXISTS 1 /* * Devicetree node: /reserved-memory/image_s@20000000 * * Node identifier: DT_N_S_reserved_memory_S_image_s_20000000 */ /* Node's full path: */ #define DT_N_S_reserved_memory_S_image_s_20000000_PATH "/reserved-memory/image_s@20000000" /* Node's name with unit-address: */ #define DT_N_S_reserved_memory_S_image_s_20000000_FULL_NAME "image_s@20000000" /* Node parent (/reserved-memory) identifier: */ #define DT_N_S_reserved_memory_S_image_s_20000000_PARENT DT_N_S_reserved_memory /* Node's index in its parent's list of children: */ #define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_NUM 0 #define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD(fn) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_reserved_memory_S_image_s_20000000_ORD 56 #define DT_N_S_reserved_memory_S_image_s_20000000_ORD_STR_SORTABLE 00056 /* Ordinals for what this node depends on directly: */ #define DT_N_S_reserved_memory_S_image_s_20000000_REQUIRES_ORDS \ 53, /* /reserved-memory */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_reserved_memory_S_image_s_20000000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_reserved_memory_S_image_s_20000000_EXISTS 1 #define DT_N_NODELABEL_sram0_s DT_N_S_reserved_memory_S_image_s_20000000 /* Macros for properties that are special in the specification: */ #define DT_N_S_reserved_memory_S_image_s_20000000_REG_NUM 1 #define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */ #define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_SIZE 90112 /* 0x16000 */ #define DT_N_S_reserved_memory_S_image_s_20000000_RANGES_NUM 0 #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_RANGE(fn) #define DT_N_S_reserved_memory_S_image_s_20000000_IRQ_NUM 0 #define DT_N_S_reserved_memory_S_image_s_20000000_IRQ_LEVEL 0 #define DT_N_S_reserved_memory_S_image_s_20000000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_reserved_memory_S_image_s_20000000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg {536870912 /* 0x20000000 */, 90112 /* 0x16000 */} #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0 536870912 #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1 90112 #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_EXISTS 1 /* * Devicetree node: /soc/crypto@50840000 * * Node identifier: DT_N_S_soc_S_crypto_50840000 * * Binding (compatible = arm,cryptocell-310): * $ZEPHYR_BASE/dts/bindings/crypto/arm,cryptocell-310.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_crypto_50840000_PATH "/soc/crypto@50840000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_crypto_50840000_FULL_NAME "crypto@50840000" /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_crypto_50840000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_crypto_50840000_CHILD_IDX 4 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_crypto_50840000_CHILD_NUM 0 #define DT_N_S_soc_S_crypto_50840000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_crypto_50840000_ORD 57 #define DT_N_S_soc_S_crypto_50840000_ORD_STR_SORTABLE 00057 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_crypto_50840000_REQUIRES_ORDS \ 6, /* /soc */ \ 7, /* /soc/interrupt-controller@e000e100 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_crypto_50840000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_crypto_50840000_EXISTS 1 #define DT_N_INST_0_nordic_cryptocell DT_N_S_soc_S_crypto_50840000 #define DT_N_INST_0_arm_cryptocell_310 DT_N_S_soc_S_crypto_50840000 #define DT_N_NODELABEL_cryptocell DT_N_S_soc_S_crypto_50840000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_crypto_50840000_REG_NUM 2 #define DT_N_S_soc_S_crypto_50840000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_REG_IDX_0_VAL_ADDRESS 1350828032 /* 0x50840000 */ #define DT_N_S_soc_S_crypto_50840000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_crypto_50840000_REG_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_REG_IDX_1_VAL_ADDRESS 1350832128 /* 0x50841000 */ #define DT_N_S_soc_S_crypto_50840000_REG_IDX_1_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_crypto_50840000_REG_NAME_wrapper_VAL_ADDRESS DT_N_S_soc_S_crypto_50840000_REG_IDX_0_VAL_ADDRESS #define DT_N_S_soc_S_crypto_50840000_REG_NAME_wrapper_VAL_SIZE DT_N_S_soc_S_crypto_50840000_REG_IDX_0_VAL_SIZE #define DT_N_S_soc_S_crypto_50840000_REG_NAME_core_VAL_ADDRESS DT_N_S_soc_S_crypto_50840000_REG_IDX_1_VAL_ADDRESS #define DT_N_S_soc_S_crypto_50840000_REG_NAME_core_VAL_SIZE DT_N_S_soc_S_crypto_50840000_REG_IDX_1_VAL_SIZE #define DT_N_S_soc_S_crypto_50840000_RANGES_NUM 0 #define DT_N_S_soc_S_crypto_50840000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_crypto_50840000_IRQ_NUM 1 #define DT_N_S_soc_S_crypto_50840000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_IRQ_IDX_0_VAL_irq 64 #define DT_N_S_soc_S_crypto_50840000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_crypto_50840000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_crypto_50840000_IRQ_LEVEL 1 #define DT_N_S_soc_S_crypto_50840000_COMPAT_MATCHES_nordic_cryptocell 1 #define DT_N_S_soc_S_crypto_50840000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_crypto_50840000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_COMPAT_MODEL_IDX_0 "cryptocell" #define DT_N_S_soc_S_crypto_50840000_COMPAT_MATCHES_arm_cryptocell_310 1 #define DT_N_S_soc_S_crypto_50840000_COMPAT_VENDOR_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_COMPAT_VENDOR_IDX_1 "ARM Ltd." #define DT_N_S_soc_S_crypto_50840000_COMPAT_MODEL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_COMPAT_MODEL_IDX_1 "cryptocell-310" #define DT_N_S_soc_S_crypto_50840000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_crypto_50840000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_crypto_50840000_P_wakeup_source 0 #define DT_N_S_soc_S_crypto_50840000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_crypto_50840000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_status "okay" #define DT_N_S_soc_S_crypto_50840000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_crypto_50840000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_crypto_50840000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_crypto_50840000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_crypto_50840000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_crypto_50840000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_crypto_50840000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_crypto_50840000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50840000, status, 0) #define DT_N_S_soc_S_crypto_50840000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50840000, status, 0) #define DT_N_S_soc_S_crypto_50840000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50840000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50840000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50840000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50840000_P_status_LEN 1 #define DT_N_S_soc_S_crypto_50840000_P_status_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_compatible {"nordic,cryptocell", "arm,cryptocell-310"} #define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_0 "nordic,cryptocell" #define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_0_STRING_UNQUOTED nordic,cryptocell #define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_0_STRING_TOKEN nordic_cryptocell #define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_CRYPTOCELL #define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_1 "arm,cryptocell-310" #define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_1_STRING_UNQUOTED arm,cryptocell-310 #define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_1_STRING_TOKEN arm_cryptocell_310 #define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_1_STRING_UPPER_TOKEN ARM_CRYPTOCELL_310 #define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50840000, compatible, 0) \ fn(DT_N_S_soc_S_crypto_50840000, compatible, 1) #define DT_N_S_soc_S_crypto_50840000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50840000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_crypto_50840000, compatible, 1) #define DT_N_S_soc_S_crypto_50840000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50840000, compatible, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_crypto_50840000, compatible, 1, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50840000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50840000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_crypto_50840000, compatible, 1, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50840000_P_compatible_LEN 2 #define DT_N_S_soc_S_crypto_50840000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_reg {1350828032 /* 0x50840000 */, 4096 /* 0x1000 */, 1350832128 /* 0x50841000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_crypto_50840000_P_reg_IDX_0 1350828032 #define DT_N_S_soc_S_crypto_50840000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_crypto_50840000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_reg_IDX_2 1350832128 #define DT_N_S_soc_S_crypto_50840000_P_reg_IDX_2_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_reg_IDX_3 4096 #define DT_N_S_soc_S_crypto_50840000_P_reg_IDX_3_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_reg_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_reg_names {"wrapper", "core"} #define DT_N_S_soc_S_crypto_50840000_P_reg_names_IDX_0 "wrapper" #define DT_N_S_soc_S_crypto_50840000_P_reg_names_IDX_0_STRING_UNQUOTED wrapper #define DT_N_S_soc_S_crypto_50840000_P_reg_names_IDX_0_STRING_TOKEN wrapper #define DT_N_S_soc_S_crypto_50840000_P_reg_names_IDX_0_STRING_UPPER_TOKEN WRAPPER #define DT_N_S_soc_S_crypto_50840000_P_reg_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_reg_names_IDX_1 "core" #define DT_N_S_soc_S_crypto_50840000_P_reg_names_IDX_1_STRING_UNQUOTED core #define DT_N_S_soc_S_crypto_50840000_P_reg_names_IDX_1_STRING_TOKEN core #define DT_N_S_soc_S_crypto_50840000_P_reg_names_IDX_1_STRING_UPPER_TOKEN CORE #define DT_N_S_soc_S_crypto_50840000_P_reg_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50840000, reg_names, 0) \ fn(DT_N_S_soc_S_crypto_50840000, reg_names, 1) #define DT_N_S_soc_S_crypto_50840000_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50840000, reg_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_crypto_50840000, reg_names, 1) #define DT_N_S_soc_S_crypto_50840000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50840000, reg_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_crypto_50840000, reg_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50840000_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50840000, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_crypto_50840000, reg_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50840000_P_reg_names_LEN 2 #define DT_N_S_soc_S_crypto_50840000_P_reg_names_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_interrupts {64 /* 0x40 */, 1 /* 0x1 */} #define DT_N_S_soc_S_crypto_50840000_P_interrupts_IDX_0 64 #define DT_N_S_soc_S_crypto_50840000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_crypto_50840000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_crypto_50840000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_crypto_50840000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/ctrlap@50006000 * * Node identifier: DT_N_S_soc_S_ctrlap_50006000 * * Binding (compatible = nordic,nrf-ctrlapperi): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-ctrlapperi.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_ctrlap_50006000_PATH "/soc/ctrlap@50006000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_ctrlap_50006000_FULL_NAME "ctrlap@50006000" /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_ctrlap_50006000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_ctrlap_50006000_CHILD_IDX 5 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_ctrlap_50006000_CHILD_NUM 0 #define DT_N_S_soc_S_ctrlap_50006000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_ctrlap_50006000_ORD 58 #define DT_N_S_soc_S_ctrlap_50006000_ORD_STR_SORTABLE 00058 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_ctrlap_50006000_REQUIRES_ORDS \ 6, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_ctrlap_50006000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_ctrlap_50006000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_ctrlapperi DT_N_S_soc_S_ctrlap_50006000 #define DT_N_NODELABEL_ctrlap DT_N_S_soc_S_ctrlap_50006000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_ctrlap_50006000_REG_NUM 1 #define DT_N_S_soc_S_ctrlap_50006000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_REG_IDX_0_VAL_ADDRESS 1342201856 /* 0x50006000 */ #define DT_N_S_soc_S_ctrlap_50006000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_ctrlap_50006000_RANGES_NUM 0 #define DT_N_S_soc_S_ctrlap_50006000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_ctrlap_50006000_IRQ_NUM 0 #define DT_N_S_soc_S_ctrlap_50006000_IRQ_LEVEL 0 #define DT_N_S_soc_S_ctrlap_50006000_COMPAT_MATCHES_nordic_nrf_ctrlapperi 1 #define DT_N_S_soc_S_ctrlap_50006000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_ctrlap_50006000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_COMPAT_MODEL_IDX_0 "nrf-ctrlapperi" #define DT_N_S_soc_S_ctrlap_50006000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_ctrlap_50006000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_ctrlap_50006000_P_wakeup_source 0 #define DT_N_S_soc_S_ctrlap_50006000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_ctrlap_50006000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_P_status "okay" #define DT_N_S_soc_S_ctrlap_50006000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_ctrlap_50006000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_ctrlap_50006000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_ctrlap_50006000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_ctrlap_50006000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_ctrlap_50006000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_ctrlap_50006000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_ctrlap_50006000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ctrlap_50006000, status, 0) #define DT_N_S_soc_S_ctrlap_50006000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ctrlap_50006000, status, 0) #define DT_N_S_soc_S_ctrlap_50006000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ctrlap_50006000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_ctrlap_50006000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ctrlap_50006000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_ctrlap_50006000_P_status_LEN 1 #define DT_N_S_soc_S_ctrlap_50006000_P_status_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_P_compatible {"nordic,nrf-ctrlapperi"} #define DT_N_S_soc_S_ctrlap_50006000_P_compatible_IDX_0 "nordic,nrf-ctrlapperi" #define DT_N_S_soc_S_ctrlap_50006000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ctrlapperi #define DT_N_S_soc_S_ctrlap_50006000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ctrlapperi #define DT_N_S_soc_S_ctrlap_50006000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CTRLAPPERI #define DT_N_S_soc_S_ctrlap_50006000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ctrlap_50006000, compatible, 0) #define DT_N_S_soc_S_ctrlap_50006000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ctrlap_50006000, compatible, 0) #define DT_N_S_soc_S_ctrlap_50006000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ctrlap_50006000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_ctrlap_50006000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ctrlap_50006000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_ctrlap_50006000_P_compatible_LEN 1 #define DT_N_S_soc_S_ctrlap_50006000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_P_reg {1342201856 /* 0x50006000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_ctrlap_50006000_P_reg_IDX_0 1342201856 #define DT_N_S_soc_S_ctrlap_50006000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_ctrlap_50006000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_P_reg_EXISTS 1 #define DT_N_S_soc_S_ctrlap_50006000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_ctrlap_50006000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/ficr@ff0000 * * Node identifier: DT_N_S_soc_S_ficr_ff0000 * * Binding (compatible = nordic,nrf-ficr): * $ZEPHYR_BASE/dts/bindings/misc/nordic,nrf-ficr.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_ficr_ff0000_PATH "/soc/ficr@ff0000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_ficr_ff0000_FULL_NAME "ficr@ff0000" /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_ficr_ff0000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_ficr_ff0000_CHILD_IDX 9 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_ficr_ff0000_CHILD_NUM 0 #define DT_N_S_soc_S_ficr_ff0000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_ficr_ff0000_ORD 59 #define DT_N_S_soc_S_ficr_ff0000_ORD_STR_SORTABLE 00059 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_ficr_ff0000_REQUIRES_ORDS \ 6, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_ficr_ff0000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_ficr_ff0000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_ficr DT_N_S_soc_S_ficr_ff0000 #define DT_N_NODELABEL_ficr DT_N_S_soc_S_ficr_ff0000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_ficr_ff0000_REG_NUM 1 #define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_VAL_ADDRESS 16711680 /* 0xff0000 */ #define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_ficr_ff0000_RANGES_NUM 0 #define DT_N_S_soc_S_ficr_ff0000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_ficr_ff0000_IRQ_NUM 0 #define DT_N_S_soc_S_ficr_ff0000_IRQ_LEVEL 0 #define DT_N_S_soc_S_ficr_ff0000_COMPAT_MATCHES_nordic_nrf_ficr 1 #define DT_N_S_soc_S_ficr_ff0000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_ficr_ff0000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_COMPAT_MODEL_IDX_0 "nrf-ficr" #define DT_N_S_soc_S_ficr_ff0000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_ficr_ff0000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_ficr_ff0000_P_wakeup_source 0 #define DT_N_S_soc_S_ficr_ff0000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_ficr_ff0000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_status "okay" #define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_ficr_ff0000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_ficr_ff0000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ff0000, status, 0) #define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ff0000, status, 0) #define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ff0000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_ficr_ff0000_P_status_LEN 1 #define DT_N_S_soc_S_ficr_ff0000_P_status_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_compatible {"nordic,nrf-ficr"} #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0 "nordic,nrf-ficr" #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ficr #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ficr #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_FICR #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0) #define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0) #define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_ficr_ff0000_P_compatible_LEN 1 #define DT_N_S_soc_S_ficr_ff0000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_reg {16711680 /* 0xff0000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_0 16711680 #define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_reg_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_ficr_ff0000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/gpiote@40031000 * * Node identifier: DT_N_S_soc_S_gpiote_40031000 * * Binding (compatible = nordic,nrf-gpiote): * $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpiote.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_gpiote_40031000_PATH "/soc/gpiote@40031000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_gpiote_40031000_FULL_NAME "gpiote@40031000" /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_gpiote_40031000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_gpiote_40031000_CHILD_IDX 7 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_gpiote_40031000_CHILD_NUM 0 #define DT_N_S_soc_S_gpiote_40031000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_gpiote_40031000_ORD 60 #define DT_N_S_soc_S_gpiote_40031000_ORD_STR_SORTABLE 00060 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_gpiote_40031000_REQUIRES_ORDS \ 6, /* /soc */ \ 7, /* /soc/interrupt-controller@e000e100 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_gpiote_40031000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_gpiote_40031000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_40031000 #define DT_N_NODELABEL_gpiote1 DT_N_S_soc_S_gpiote_40031000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_gpiote_40031000_REG_NUM 1 #define DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_VAL_ADDRESS 1073942528 /* 0x40031000 */ #define DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_gpiote_40031000_RANGES_NUM 0 #define DT_N_S_soc_S_gpiote_40031000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_gpiote_40031000_IRQ_NUM 1 #define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_irq 49 #define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_priority 5 #define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_gpiote_40031000_IRQ_LEVEL 1 #define DT_N_S_soc_S_gpiote_40031000_COMPAT_MATCHES_nordic_nrf_gpiote 1 #define DT_N_S_soc_S_gpiote_40031000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_gpiote_40031000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_COMPAT_MODEL_IDX_0 "nrf-gpiote" #define DT_N_S_soc_S_gpiote_40031000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_gpiote_40031000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_gpiote_40031000_P_wakeup_source 0 #define DT_N_S_soc_S_gpiote_40031000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_gpiote_40031000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_status "disabled" #define DT_N_S_soc_S_gpiote_40031000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_gpiote_40031000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_gpiote_40031000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_gpiote_40031000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_gpiote_40031000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_gpiote_40031000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_40031000, status, 0) #define DT_N_S_soc_S_gpiote_40031000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_40031000, status, 0) #define DT_N_S_soc_S_gpiote_40031000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_40031000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_40031000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_40031000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_40031000_P_status_LEN 1 #define DT_N_S_soc_S_gpiote_40031000_P_status_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_compatible {"nordic,nrf-gpiote"} #define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0 "nordic,nrf-gpiote" #define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpiote #define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpiote #define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIOTE #define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_40031000, compatible, 0) #define DT_N_S_soc_S_gpiote_40031000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_40031000, compatible, 0) #define DT_N_S_soc_S_gpiote_40031000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_40031000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_40031000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_40031000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_40031000_P_compatible_LEN 1 #define DT_N_S_soc_S_gpiote_40031000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_reg {1073942528 /* 0x40031000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_0 1073942528 #define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_reg_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_interrupts {49 /* 0x31 */, 5 /* 0x5 */} #define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_0 49 #define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_1 5 #define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_gpiote_40031000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_gpiote_40031000_P_instance 1 #define DT_N_S_soc_S_gpiote_40031000_P_instance_EXISTS 1 /* * Devicetree node: /soc/memory@20000000 * * Node identifier: DT_N_S_soc_S_memory_20000000 * * Binding (compatible = mmio-sram): * $ZEPHYR_BASE/dts/bindings/sram/mmio-sram.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_memory_20000000_PATH "/soc/memory@20000000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_memory_20000000_FULL_NAME "memory@20000000" /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_memory_20000000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_memory_20000000_CHILD_IDX 2 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_memory_20000000_CHILD_NUM 0 #define DT_N_S_soc_S_memory_20000000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_memory_20000000_ORD 61 #define DT_N_S_soc_S_memory_20000000_ORD_STR_SORTABLE 00061 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_memory_20000000_REQUIRES_ORDS \ 6, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_memory_20000000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_memory_20000000_EXISTS 1 #define DT_N_INST_0_mmio_sram DT_N_S_soc_S_memory_20000000 #define DT_N_NODELABEL_sram0 DT_N_S_soc_S_memory_20000000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_memory_20000000_REG_NUM 1 #define DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */ #define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */ #define DT_N_S_soc_S_memory_20000000_RANGES_NUM 0 #define DT_N_S_soc_S_memory_20000000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_memory_20000000_IRQ_NUM 0 #define DT_N_S_soc_S_memory_20000000_IRQ_LEVEL 0 #define DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram 1 #define DT_N_S_soc_S_memory_20000000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_memory_20000000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_memory_20000000_P_wakeup_source 0 #define DT_N_S_soc_S_memory_20000000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_memory_20000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_compatible {"mmio-sram"} #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0 "mmio-sram" #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UNQUOTED mmio-sram #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_TOKEN mmio_sram #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UPPER_TOKEN MMIO_SRAM #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_20000000, compatible, 0) #define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_20000000, compatible, 0) #define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_memory_20000000_P_compatible_LEN 1 #define DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_reg {536870912 /* 0x20000000 */, 262144 /* 0x40000 */} #define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0 536870912 #define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1 262144 #define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_reg_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_memory_20000000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/spu@50003000 * * Node identifier: DT_N_S_soc_S_spu_50003000 * * Binding (compatible = nordic,nrf-spu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-spu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_spu_50003000_PATH "/soc/spu@50003000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_spu_50003000_FULL_NAME "spu@50003000" /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_spu_50003000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_spu_50003000_CHILD_IDX 8 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_spu_50003000_CHILD_NUM 0 #define DT_N_S_soc_S_spu_50003000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_spu_50003000_ORD 62 #define DT_N_S_soc_S_spu_50003000_ORD_STR_SORTABLE 00062 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spu_50003000_REQUIRES_ORDS \ 6, /* /soc */ \ 7, /* /soc/interrupt-controller@e000e100 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_spu_50003000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_spu_50003000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_spu DT_N_S_soc_S_spu_50003000 #define DT_N_NODELABEL_spu DT_N_S_soc_S_spu_50003000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_spu_50003000_REG_NUM 1 #define DT_N_S_soc_S_spu_50003000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_REG_IDX_0_VAL_ADDRESS 1342189568 /* 0x50003000 */ #define DT_N_S_soc_S_spu_50003000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_spu_50003000_RANGES_NUM 0 #define DT_N_S_soc_S_spu_50003000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_spu_50003000_IRQ_NUM 1 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_irq 3 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_spu_50003000_IRQ_LEVEL 1 #define DT_N_S_soc_S_spu_50003000_COMPAT_MATCHES_nordic_nrf_spu 1 #define DT_N_S_soc_S_spu_50003000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_spu_50003000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_COMPAT_MODEL_IDX_0 "nrf-spu" #define DT_N_S_soc_S_spu_50003000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_spu_50003000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_spu_50003000_P_wakeup_source 0 #define DT_N_S_soc_S_spu_50003000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_spu_50003000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_status "okay" #define DT_N_S_soc_S_spu_50003000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_spu_50003000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_spu_50003000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_spu_50003000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_spu_50003000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_spu_50003000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_spu_50003000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, status, 0) #define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, status, 0) #define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_spu_50003000_P_status_LEN 1 #define DT_N_S_soc_S_spu_50003000_P_status_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_compatible {"nordic,nrf-spu"} #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0 "nordic,nrf-spu" #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spu #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spu #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPU #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, compatible, 0) #define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, compatible, 0) #define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_spu_50003000_P_compatible_LEN 1 #define DT_N_S_soc_S_spu_50003000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_reg {1342189568 /* 0x50003000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_spu_50003000_P_reg_IDX_0 1342189568 #define DT_N_S_soc_S_spu_50003000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_spu_50003000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_reg_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_interrupts {3 /* 0x3 */, 1 /* 0x1 */} #define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_0 3 #define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_spu_50003000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/timer@e000e010 * * Node identifier: DT_N_S_soc_S_timer_e000e010 * * Binding (compatible = arm,armv8m-systick): * $ZEPHYR_BASE/dts/bindings/timer/arm,armv8m-systick.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_timer_e000e010_PATH "/soc/timer@e000e010" /* Node's name with unit-address: */ #define DT_N_S_soc_S_timer_e000e010_FULL_NAME "timer@e000e010" /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timer_e000e010_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_timer_e000e010_CHILD_IDX 1 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_timer_e000e010_CHILD_NUM 0 #define DT_N_S_soc_S_timer_e000e010_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD(fn) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_timer_e000e010_ORD 63 #define DT_N_S_soc_S_timer_e000e010_ORD_STR_SORTABLE 00063 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS \ 6, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timer_e000e010_EXISTS 1 #define DT_N_INST_0_arm_armv8m_systick DT_N_S_soc_S_timer_e000e010 #define DT_N_NODELABEL_systick DT_N_S_soc_S_timer_e000e010 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timer_e000e010_REG_NUM 1 #define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */ #define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */ #define DT_N_S_soc_S_timer_e000e010_RANGES_NUM 0 #define DT_N_S_soc_S_timer_e000e010_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timer_e000e010_IRQ_NUM 0 #define DT_N_S_soc_S_timer_e000e010_IRQ_LEVEL 0 #define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv8m_systick 1 #define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0 "ARM Ltd." #define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0 "armv8m-systick" #define DT_N_S_soc_S_timer_e000e010_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_timer_e000e010_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_timer_e000e010_P_wakeup_source 0 #define DT_N_S_soc_S_timer_e000e010_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_status "disabled" #define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timer_e000e010_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timer_e000e010_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timer_e000e010_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, status, 0) #define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, status, 0) #define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_timer_e000e010_P_status_LEN 1 #define DT_N_S_soc_S_timer_e000e010_P_status_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_compatible {"arm,armv8m-systick"} #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0 "arm,armv8m-systick" #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-systick #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_systick #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_SYSTICK #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0) #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0) #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN 1 #define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */} #define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744 #define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16 #define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/uicr@ff8000 * * Node identifier: DT_N_S_soc_S_uicr_ff8000 * * Binding (compatible = nordic,nrf-uicr): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-uicr.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_uicr_ff8000_PATH "/soc/uicr@ff8000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_uicr_ff8000_FULL_NAME "uicr@ff8000" /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_uicr_ff8000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_uicr_ff8000_CHILD_IDX 10 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_uicr_ff8000_CHILD_NUM 0 #define DT_N_S_soc_S_uicr_ff8000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_uicr_ff8000_ORD 64 #define DT_N_S_soc_S_uicr_ff8000_ORD_STR_SORTABLE 00064 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_uicr_ff8000_REQUIRES_ORDS \ 6, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_uicr_ff8000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_uicr_ff8000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_uicr DT_N_S_soc_S_uicr_ff8000 #define DT_N_NODELABEL_uicr DT_N_S_soc_S_uicr_ff8000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_uicr_ff8000_REG_NUM 1 #define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_VAL_ADDRESS 16744448 /* 0xff8000 */ #define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_uicr_ff8000_RANGES_NUM 0 #define DT_N_S_soc_S_uicr_ff8000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_uicr_ff8000_IRQ_NUM 0 #define DT_N_S_soc_S_uicr_ff8000_IRQ_LEVEL 0 #define DT_N_S_soc_S_uicr_ff8000_COMPAT_MATCHES_nordic_nrf_uicr 1 #define DT_N_S_soc_S_uicr_ff8000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_uicr_ff8000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_COMPAT_MODEL_IDX_0 "nrf-uicr" #define DT_N_S_soc_S_uicr_ff8000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_uicr_ff8000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_uicr_ff8000_P_wakeup_source 0 #define DT_N_S_soc_S_uicr_ff8000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_uicr_ff8000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_status "okay" #define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_uicr_ff8000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_uicr_ff8000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_ff8000, status, 0) #define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_ff8000, status, 0) #define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_ff8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_uicr_ff8000_P_status_LEN 1 #define DT_N_S_soc_S_uicr_ff8000_P_status_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_compatible {"nordic,nrf-uicr"} #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0 "nordic,nrf-uicr" #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uicr #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uicr #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UICR #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0) #define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0) #define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_uicr_ff8000_P_compatible_LEN 1 #define DT_N_S_soc_S_uicr_ff8000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_reg {16744448 /* 0xff8000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_0 16744448 #define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_reg_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_uicr_ff8000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_nfct_pins_as_gpios 0 #define DT_N_S_soc_S_uicr_ff8000_P_nfct_pins_as_gpios_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_gpio_as_nreset 0 #define DT_N_S_soc_S_uicr_ff8000_P_gpio_as_nreset_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/adc@e000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_adc_e000 * * Binding (compatible = nordic,nrf-saadc): * $ZEPHYR_BASE/dts/bindings/adc/nordic,nrf-saadc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PATH "/soc/peripheral@50000000/adc@e000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FULL_NAME "adc@e000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_CHILD_IDX 1 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_ORD 65 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_ORD_STR_SORTABLE 00065 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_saadc DT_N_S_soc_S_peripheral_50000000_S_adc_e000 #define DT_N_NODELABEL_adc DT_N_S_soc_S_peripheral_50000000_S_adc_e000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_VAL_ADDRESS 1342234624 /* 0x5000e000 */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_irq 14 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MATCHES_nordic_nrf_saadc 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MODEL_IDX_0 "nrf-saadc" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible {"nordic,nrf-saadc"} #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0 "nordic,nrf-saadc" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-saadc #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_saadc #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SAADC #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg {57344 /* 0xe000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_0 57344 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts {14 /* 0xe */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_0 14 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/clock@5000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_clock_5000 * * Binding (compatible = nordic,nrf-clock): * $ZEPHYR_BASE/dts/bindings/clock/nordic,nrf-clock.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PATH "/soc/peripheral@50000000/clock@5000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FULL_NAME "clock@5000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_CHILD_IDX 34 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_ORD 66 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_ORD_STR_SORTABLE 00066 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_clock DT_N_S_soc_S_peripheral_50000000_S_clock_5000 #define DT_N_NODELABEL_clock DT_N_S_soc_S_peripheral_50000000_S_clock_5000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_irq 5 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MATCHES_nordic_nrf_clock 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MODEL_IDX_0 "nrf-clock" #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible {"nordic,nrf-clock"} #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0 "nordic,nrf-clock" #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-clock #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_clock #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CLOCK #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_0 20480 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_0 5 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/dppic@17000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_dppic_17000 * * Binding (compatible = nordic,nrf-dppic): * $ZEPHYR_BASE/dts/bindings/misc/nordic,nrf-dppic.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PATH "/soc/peripheral@50000000/dppic@17000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FULL_NAME "dppic@17000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_CHILD_IDX 2 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_ORD 67 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_ORD_STR_SORTABLE 00067 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REQUIRES_ORDS \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_dppic DT_N_S_soc_S_peripheral_50000000_S_dppic_17000 #define DT_N_NODELABEL_dppic DT_N_S_soc_S_peripheral_50000000_S_dppic_17000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_VAL_ADDRESS 1342271488 /* 0x50017000 */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MATCHES_nordic_nrf_dppic 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MODEL_IDX_0 "nrf-dppic" #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible {"nordic,nrf-dppic"} #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0 "nordic,nrf-dppic" #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-dppic #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_dppic #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_DPPIC #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg {94208 /* 0x17000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_0 94208 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/egu@1b000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1b000 * * Binding (compatible = nordic,nrf-egu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PATH "/soc/peripheral@50000000/egu@1b000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FULL_NAME "egu@1b000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_CHILD_IDX 3 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_ORD 68 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_ORD_STR_SORTABLE 00068 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1b000 #define DT_N_NODELABEL_egu0 DT_N_S_soc_S_peripheral_50000000_S_egu_1b000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_VAL_ADDRESS 1342287872 /* 0x5001b000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_irq 27 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MATCHES_nordic_nrf_egu 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MODEL_IDX_0 "nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible {"nordic,nrf-egu"} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0 "nordic,nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg {110592 /* 0x1b000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_0 110592 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts {27 /* 0x1b */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_0 27 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/egu@1c000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1c000 * * Binding (compatible = nordic,nrf-egu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PATH "/soc/peripheral@50000000/egu@1c000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FULL_NAME "egu@1c000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_CHILD_IDX 4 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_ORD 69 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_ORD_STR_SORTABLE 00069 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1c000 #define DT_N_NODELABEL_egu1 DT_N_S_soc_S_peripheral_50000000_S_egu_1c000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_VAL_ADDRESS 1342291968 /* 0x5001c000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_irq 28 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MATCHES_nordic_nrf_egu 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MODEL_IDX_0 "nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible {"nordic,nrf-egu"} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0 "nordic,nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg {114688 /* 0x1c000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_0 114688 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts {28 /* 0x1c */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_0 28 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/egu@1d000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1d000 * * Binding (compatible = nordic,nrf-egu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PATH "/soc/peripheral@50000000/egu@1d000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FULL_NAME "egu@1d000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_CHILD_IDX 5 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_ORD 70 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_ORD_STR_SORTABLE 00070 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_EXISTS 1 #define DT_N_INST_2_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1d000 #define DT_N_NODELABEL_egu2 DT_N_S_soc_S_peripheral_50000000_S_egu_1d000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_VAL_ADDRESS 1342296064 /* 0x5001d000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_irq 29 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MATCHES_nordic_nrf_egu 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MODEL_IDX_0 "nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible {"nordic,nrf-egu"} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0 "nordic,nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg {118784 /* 0x1d000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_0 118784 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts {29 /* 0x1d */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_0 29 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/egu@1e000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1e000 * * Binding (compatible = nordic,nrf-egu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PATH "/soc/peripheral@50000000/egu@1e000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FULL_NAME "egu@1e000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_CHILD_IDX 6 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_ORD 71 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_ORD_STR_SORTABLE 00071 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_EXISTS 1 #define DT_N_INST_3_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1e000 #define DT_N_NODELABEL_egu3 DT_N_S_soc_S_peripheral_50000000_S_egu_1e000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_VAL_ADDRESS 1342300160 /* 0x5001e000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_irq 30 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MATCHES_nordic_nrf_egu 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MODEL_IDX_0 "nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible {"nordic,nrf-egu"} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0 "nordic,nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg {122880 /* 0x1e000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_0 122880 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts {30 /* 0x1e */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_0 30 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/egu@1f000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1f000 * * Binding (compatible = nordic,nrf-egu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PATH "/soc/peripheral@50000000/egu@1f000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FULL_NAME "egu@1f000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_CHILD_IDX 7 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_ORD 72 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_ORD_STR_SORTABLE 00072 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_EXISTS 1 #define DT_N_INST_4_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1f000 #define DT_N_NODELABEL_egu4 DT_N_S_soc_S_peripheral_50000000_S_egu_1f000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_VAL_ADDRESS 1342304256 /* 0x5001f000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_irq 31 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MATCHES_nordic_nrf_egu 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MODEL_IDX_0 "nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible {"nordic,nrf-egu"} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0 "nordic,nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg {126976 /* 0x1f000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_0 126976 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts {31 /* 0x1f */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_0 31 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/egu@20000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_20000 * * Binding (compatible = nordic,nrf-egu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PATH "/soc/peripheral@50000000/egu@20000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FULL_NAME "egu@20000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_CHILD_IDX 8 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_ORD 73 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_ORD_STR_SORTABLE 00073 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_EXISTS 1 #define DT_N_INST_5_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_20000 #define DT_N_NODELABEL_egu5 DT_N_S_soc_S_peripheral_50000000_S_egu_20000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_VAL_ADDRESS 1342308352 /* 0x50020000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_irq 32 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MATCHES_nordic_nrf_egu 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MODEL_IDX_0 "nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible {"nordic,nrf-egu"} #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0 "nordic,nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg {131072 /* 0x20000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_0 131072 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts {32 /* 0x20 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_0 32 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2c@8000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_8000 * * Binding (compatible = nordic,nrf-twim): * $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PATH "/soc/peripheral@50000000/i2c@8000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FULL_NAME "i2c@8000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_CHILD_IDX 19 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_ORD 74 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_ORD_STR_SORTABLE 00074 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_8000 #define DT_N_NODELABEL_i2c0 DT_N_S_soc_S_peripheral_50000000_S_i2c_8000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_irq 8 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MATCHES_nordic_nrf_twim 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MODEL_IDX_0 "nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible {"nordic,nrf-twim"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0 "nordic,nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_0 32768 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_0 8 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_clock_frequency 100000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_clock_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_sq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_sq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_cq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_cq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_easydma_maxcnt_bits 13 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_concat_buf_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_concat_buf_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_flash_buf_max_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_flash_buf_max_size_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2c@9000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_9000 * * Binding (compatible = nordic,nrf-twim): * $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PATH "/soc/peripheral@50000000/i2c@9000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FULL_NAME "i2c@9000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_CHILD_IDX 20 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_ORD 75 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_ORD_STR_SORTABLE 00075 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_EXISTS 1 #define DT_N_INST_2_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_9000 #define DT_N_NODELABEL_i2c1 DT_N_S_soc_S_peripheral_50000000_S_i2c_9000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_irq 9 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MATCHES_nordic_nrf_twim 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MODEL_IDX_0 "nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible {"nordic,nrf-twim"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0 "nordic,nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_0 36864 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_0 9 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_clock_frequency 100000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_clock_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_sq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_sq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_cq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_cq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_easydma_maxcnt_bits 13 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_concat_buf_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_concat_buf_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_flash_buf_max_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_flash_buf_max_size_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2c@b000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_b000 * * Binding (compatible = nordic,nrf-twim): * $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PATH "/soc/peripheral@50000000/i2c@b000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FULL_NAME "i2c@b000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_CHILD_IDX 22 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_ORD 76 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_ORD_STR_SORTABLE 00076 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_EXISTS 1 #define DT_N_INST_3_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_b000 #define DT_N_NODELABEL_i2c3 DT_N_S_soc_S_peripheral_50000000_S_i2c_b000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_irq 11 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MATCHES_nordic_nrf_twim 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MODEL_IDX_0 "nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible {"nordic,nrf-twim"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0 "nordic,nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_0 45056 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_0 11 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_clock_frequency 100000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_clock_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_sq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_sq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_cq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_cq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_easydma_maxcnt_bits 13 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_concat_buf_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_concat_buf_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_flash_buf_max_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_flash_buf_max_size_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2s@28000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2s_28000 * * Binding (compatible = nordic,nrf-i2s): * $ZEPHYR_BASE/dts/bindings/i2s/nordic,nrf-i2s.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PATH "/soc/peripheral@50000000/i2s@28000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FULL_NAME "i2s@28000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_CHILD_IDX 10 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_ORD 77 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_ORD_STR_SORTABLE 00077 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_i2s DT_N_S_soc_S_peripheral_50000000_S_i2s_28000 #define DT_N_NODELABEL_i2s0 DT_N_S_soc_S_peripheral_50000000_S_i2s_28000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_VAL_ADDRESS 1342341120 /* 0x50028000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_irq 40 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MATCHES_nordic_nrf_i2s 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MODEL_IDX_0 "nrf-i2s" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible {"nordic,nrf-i2s"} #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0 "nordic,nrf-i2s" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-i2s #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_i2s #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_I2S #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg {163840 /* 0x28000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_0 163840 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts {40 /* 0x28 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_0 40 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source "PCLK32M_HFXO" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_TOKEN PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_IDX_0 "PCLK32M_HFXO" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_VAL_PCLK32M_HFXO_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/ipc@2a000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000 * * Binding (compatible = nordic,nrf-ipc): * $ZEPHYR_BASE/dts/bindings/ipc/nordic,nrf-ipc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_PATH "/soc/peripheral@50000000/ipc@2a000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FULL_NAME "ipc@2a000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_CHILD_IDX 9 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_ORD 78 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_ORD_STR_SORTABLE 00078 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_ipc DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000 #define DT_N_NODELABEL_ipc DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REG_IDX_0_VAL_ADDRESS 1342349312 /* 0x5002a000 */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_VAL_irq 42 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_COMPAT_MATCHES_nordic_nrf_ipc 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_COMPAT_MODEL_IDX_0 "nrf-ipc" #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible {"nordic,nrf-ipc"} #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_IDX_0 "nordic,nrf-ipc" #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ipc #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ipc #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_IPC #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg {172032 /* 0x2a000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_IDX_0 172032 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts {42 /* 0x2a */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_IDX_0 42 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/kmu@39000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_kmu_39000 * * Binding (compatible = nordic,nrf-kmu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-kmu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PATH "/soc/peripheral@50000000/kmu@39000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FULL_NAME "kmu@39000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_CHILD_IDX 11 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_ORD 79 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_ORD_STR_SORTABLE 00079 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_kmu DT_N_S_soc_S_peripheral_50000000_S_kmu_39000 #define DT_N_NODELABEL_kmu DT_N_S_soc_S_peripheral_50000000_S_kmu_39000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_VAL_ADDRESS 1342410752 /* 0x50039000 */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_irq 57 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MATCHES_nordic_nrf_kmu 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MODEL_IDX_0 "nrf-kmu" #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible {"nordic,nrf-kmu"} #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0 "nordic,nrf-kmu" #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-kmu #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_kmu #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_KMU #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_0 233472 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts {57 /* 0x39 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_0 57 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/pdm@26000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pdm_26000 * * Binding (compatible = nordic,nrf-pdm): * $ZEPHYR_BASE/dts/bindings/audio/nordic,nrf-pdm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PATH "/soc/peripheral@50000000/pdm@26000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FULL_NAME "pdm@26000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_CHILD_IDX 12 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_ORD 80 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_ORD_STR_SORTABLE 00080 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_pdm DT_N_S_soc_S_peripheral_50000000_S_pdm_26000 #define DT_N_NODELABEL_pdm0 DT_N_S_soc_S_peripheral_50000000_S_pdm_26000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_VAL_ADDRESS 1342332928 /* 0x50026000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_irq 38 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MATCHES_nordic_nrf_pdm 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MODEL_IDX_0 "nrf-pdm" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible {"nordic,nrf-pdm"} #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0 "nordic,nrf-pdm" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pdm #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pdm #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PDM #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg {155648 /* 0x26000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_0 155648 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts {38 /* 0x26 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_0 38 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source "PCLK32M_HFXO" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_TOKEN PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_IDX_0 "PCLK32M_HFXO" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_VAL_PCLK32M_HFXO_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_queue_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_queue_size_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/pwm@22000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_22000 * * Binding (compatible = nordic,nrf-pwm): * $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PATH "/soc/peripheral@50000000/pwm@22000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FULL_NAME "pwm@22000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_CHILD_IDX 28 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_ORD 81 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_ORD_STR_SORTABLE 00081 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_22000 #define DT_N_NODELABEL_pwm1 DT_N_S_soc_S_peripheral_50000000_S_pwm_22000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_VAL_ADDRESS 1342316544 /* 0x50022000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_irq 34 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MATCHES_nordic_nrf_pwm 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MODEL_IDX_0 "nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible {"nordic,nrf-pwm"} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0 "nordic,nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg {139264 /* 0x22000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_0 139264 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts {34 /* 0x22 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_0 34 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_center_aligned 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_center_aligned_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/pwm@23000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_23000 * * Binding (compatible = nordic,nrf-pwm): * $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PATH "/soc/peripheral@50000000/pwm@23000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FULL_NAME "pwm@23000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_CHILD_IDX 29 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_ORD 82 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_ORD_STR_SORTABLE 00082 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_EXISTS 1 #define DT_N_INST_2_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_23000 #define DT_N_NODELABEL_pwm2 DT_N_S_soc_S_peripheral_50000000_S_pwm_23000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_VAL_ADDRESS 1342320640 /* 0x50023000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_irq 35 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MATCHES_nordic_nrf_pwm 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MODEL_IDX_0 "nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible {"nordic,nrf-pwm"} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0 "nordic,nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg {143360 /* 0x23000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_0 143360 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts {35 /* 0x23 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_0 35 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_center_aligned 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_center_aligned_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/pwm@24000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_24000 * * Binding (compatible = nordic,nrf-pwm): * $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PATH "/soc/peripheral@50000000/pwm@24000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FULL_NAME "pwm@24000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_CHILD_IDX 30 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_ORD 83 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_ORD_STR_SORTABLE 00083 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_EXISTS 1 #define DT_N_INST_3_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_24000 #define DT_N_NODELABEL_pwm3 DT_N_S_soc_S_peripheral_50000000_S_pwm_24000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_VAL_ADDRESS 1342324736 /* 0x50024000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_irq 36 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MATCHES_nordic_nrf_pwm 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MODEL_IDX_0 "nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible {"nordic,nrf-pwm"} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0 "nordic,nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg {147456 /* 0x24000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_0 147456 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts {36 /* 0x24 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_0 36 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_center_aligned 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_center_aligned_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/regulator@4000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_4000 * * Binding (compatible = nordic,nrf-regulators): * $ZEPHYR_BASE/dts/bindings/power/nordic,nrf-regulators.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PATH "/soc/peripheral@50000000/regulator@4000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FULL_NAME "regulator@4000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_CHILD_IDX 13 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_ORD 84 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_ORD_STR_SORTABLE 00084 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REQUIRES_ORDS \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_regulators DT_N_S_soc_S_peripheral_50000000_S_regulator_4000 #define DT_N_NODELABEL_regulators DT_N_S_soc_S_peripheral_50000000_S_regulator_4000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_VAL_ADDRESS 1342193664 /* 0x50004000 */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MATCHES_nordic_nrf_regulators 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MODEL_IDX_0 "nrf-regulators" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible {"nordic,nrf-regulators"} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0 "nordic,nrf-regulators" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-regulators #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_regulators #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_REGULATORS #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg {16384 /* 0x4000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_0 16384 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/rtc@14000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_rtc_14000 * * Binding (compatible = nordic,nrf-rtc): * $ZEPHYR_BASE/dts/bindings/rtc/nordic,nrf-rtc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PATH "/soc/peripheral@50000000/rtc@14000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FULL_NAME "rtc@14000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_CHILD_IDX 32 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_ORD 85 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_ORD_STR_SORTABLE 00085 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_rtc DT_N_S_soc_S_peripheral_50000000_S_rtc_14000 #define DT_N_NODELABEL_rtc0 DT_N_S_soc_S_peripheral_50000000_S_rtc_14000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_VAL_ADDRESS 1342259200 /* 0x50014000 */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_irq 20 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MATCHES_nordic_nrf_rtc 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MODEL_IDX_0 "nrf-rtc" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible {"nordic,nrf-rtc"} #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0 "nordic,nrf-rtc" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-rtc #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg {81920 /* 0x14000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_0 81920 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts {20 /* 0x14 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_0 20 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_clock_frequency 32768 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_clock_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_prescaler 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_prescaler_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_cc_num 4 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_cc_num_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_ppi_wrap 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_ppi_wrap_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_fixed_top 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_fixed_top_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zli 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zli_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/rtc@15000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_rtc_15000 * * Binding (compatible = nordic,nrf-rtc): * $ZEPHYR_BASE/dts/bindings/rtc/nordic,nrf-rtc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PATH "/soc/peripheral@50000000/rtc@15000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FULL_NAME "rtc@15000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_CHILD_IDX 33 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_ORD 86 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_ORD_STR_SORTABLE 00086 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_rtc DT_N_S_soc_S_peripheral_50000000_S_rtc_15000 #define DT_N_NODELABEL_rtc1 DT_N_S_soc_S_peripheral_50000000_S_rtc_15000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_VAL_ADDRESS 1342263296 /* 0x50015000 */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_irq 21 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MATCHES_nordic_nrf_rtc 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MODEL_IDX_0 "nrf-rtc" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible {"nordic,nrf-rtc"} #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0 "nordic,nrf-rtc" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-rtc #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg {86016 /* 0x15000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_0 86016 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts {21 /* 0x15 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_0 21 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_clock_frequency 32768 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_clock_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_prescaler 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_prescaler_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_cc_num 4 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_cc_num_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_ppi_wrap 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_ppi_wrap_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_fixed_top 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_fixed_top_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zli 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zli_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/spi@8000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_8000 * * Binding (compatible = nordic,nrf-spim): * $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PATH "/soc/peripheral@50000000/spi@8000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FULL_NAME "spi@8000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_CHILD_IDX 23 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_ORD 87 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_ORD_STR_SORTABLE 00087 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_8000 #define DT_N_NODELABEL_spi0 DT_N_S_soc_S_peripheral_50000000_S_spi_8000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_irq 8 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MATCHES_nordic_nrf_spim 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MODEL_IDX_0 "nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible {"nordic,nrf-spim"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0 "nordic,nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_0 32768 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_0 8 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_max_frequency 8000000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_overrun_character 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_overrun_character_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_easydma_maxcnt_bits 13 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_anomaly_58_workaround 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_anomaly_58_workaround_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_rx_delay_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_rx_delay_supported_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/spi@9000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_9000 * * Binding (compatible = nordic,nrf-spim): * $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PATH "/soc/peripheral@50000000/spi@9000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FULL_NAME "spi@9000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_CHILD_IDX 24 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_ORD 88 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_ORD_STR_SORTABLE 00088 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_EXISTS 1 #define DT_N_INST_2_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_9000 #define DT_N_NODELABEL_spi1 DT_N_S_soc_S_peripheral_50000000_S_spi_9000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_irq 9 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MATCHES_nordic_nrf_spim 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MODEL_IDX_0 "nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible {"nordic,nrf-spim"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0 "nordic,nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_0 36864 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_0 9 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_max_frequency 8000000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_overrun_character 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_overrun_character_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_easydma_maxcnt_bits 13 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_anomaly_58_workaround 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_anomaly_58_workaround_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_rx_delay_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_rx_delay_supported_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/spi@a000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_a000 * * Binding (compatible = nordic,nrf-spim): * $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PATH "/soc/peripheral@50000000/spi@a000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FULL_NAME "spi@a000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_CHILD_IDX 25 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_ORD 89 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_ORD_STR_SORTABLE 00089 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_EXISTS 1 #define DT_N_INST_3_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_a000 #define DT_N_NODELABEL_spi2 DT_N_S_soc_S_peripheral_50000000_S_spi_a000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_VAL_ADDRESS 1342218240 /* 0x5000a000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_irq 10 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MATCHES_nordic_nrf_spim 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MODEL_IDX_0 "nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible {"nordic,nrf-spim"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0 "nordic,nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_0 40960 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_0 10 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_max_frequency 8000000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_overrun_character 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_overrun_character_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_easydma_maxcnt_bits 13 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_anomaly_58_workaround 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_anomaly_58_workaround_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_supported_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/timer@f000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_f000 * * Binding (compatible = nordic,nrf-timer): * $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PATH "/soc/peripheral@50000000/timer@f000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FULL_NAME "timer@f000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_CHILD_IDX 37 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_ORD 90 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_ORD_STR_SORTABLE 00090 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_f000 #define DT_N_NODELABEL_timer0 DT_N_S_soc_S_peripheral_50000000_S_timer_f000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_VAL_ADDRESS 1342238720 /* 0x5000f000 */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_irq 15 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MATCHES_nordic_nrf_timer 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MODEL_IDX_0 "nrf-timer" #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible {"nordic,nrf-timer"} #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0 "nordic,nrf-timer" #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg {61440 /* 0xf000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_0 61440 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts {15 /* 0xf */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_0 15 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_cc_num 6 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_cc_num_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_bit_width 32 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_bit_width_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_frequency 16000000 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_prescaler 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_prescaler_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zli 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zli_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/timer@11000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_11000 * * Binding (compatible = nordic,nrf-timer): * $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PATH "/soc/peripheral@50000000/timer@11000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FULL_NAME "timer@11000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_CHILD_IDX 39 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_ORD 91 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_ORD_STR_SORTABLE 00091 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_EXISTS 1 #define DT_N_INST_2_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_11000 #define DT_N_NODELABEL_timer2 DT_N_S_soc_S_peripheral_50000000_S_timer_11000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_VAL_ADDRESS 1342246912 /* 0x50011000 */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_irq 17 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MATCHES_nordic_nrf_timer 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MODEL_IDX_0 "nrf-timer" #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible {"nordic,nrf-timer"} #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0 "nordic,nrf-timer" #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg {69632 /* 0x11000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_0 69632 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts {17 /* 0x11 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_0 17 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_cc_num 6 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_cc_num_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_bit_width 32 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_bit_width_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_frequency 16000000 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_prescaler 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_prescaler_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zli 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zli_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/uart@8000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_8000 * * Binding (compatible = nordic,nrf-uarte): * $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PATH "/soc/peripheral@50000000/uart@8000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FULL_NAME "uart@8000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_CHILD_IDX 15 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_ORD 92 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_ORD_STR_SORTABLE 00092 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ \ 40, /* /pin-controller/uart0_default */ \ 43, /* /pin-controller/uart0_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_8000 #define DT_N_NODELABEL_uart0 DT_N_S_soc_S_peripheral_50000000_S_uart_8000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_irq 8 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MATCHES_nordic_nrf_uarte 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MODEL_IDX_0 "nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart0_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_uart0_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible {"nordic,nrf-uarte"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0 "nordic,nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_0 32768 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_0 8 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed 115200 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed_ENUM_IDX 12 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed_ENUM_VAL_115200_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_hw_flow_control 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart0_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart0_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_uart0_sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_uart0_sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_disable_rx 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_disable_rx_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/uart@9000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_9000 * * Binding (compatible = nordic,nrf-uarte): * $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PATH "/soc/peripheral@50000000/uart@9000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FULL_NAME "uart@9000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_CHILD_IDX 16 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_ORD 93 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_ORD_STR_SORTABLE 00093 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ \ 45, /* /pin-controller/uart1_default */ \ 48, /* /pin-controller/uart1_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_9000 #define DT_N_NODELABEL_uart1 DT_N_S_soc_S_peripheral_50000000_S_uart_9000 #define DT_N_NODELABEL_arduino_serial DT_N_S_soc_S_peripheral_50000000_S_uart_9000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_irq 9 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MATCHES_nordic_nrf_uarte 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MODEL_IDX_0 "nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart1_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_uart1_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible {"nordic,nrf-uarte"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0 "nordic,nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_0 36864 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_0 9 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_current_speed 115200 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_current_speed_ENUM_IDX 12 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_current_speed_ENUM_VAL_115200_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_current_speed_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_hw_flow_control 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart1_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart1_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_uart1_sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_uart1_sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_disable_rx 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_disable_rx_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/uart@a000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_a000 * * Binding (compatible = nordic,nrf-uarte): * $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_PATH "/soc/peripheral@50000000/uart@a000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FULL_NAME "uart@a000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_CHILD_IDX 17 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_ORD 94 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_ORD_STR_SORTABLE 00094 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_EXISTS 1 #define DT_N_INST_2_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_a000 #define DT_N_NODELABEL_uart2 DT_N_S_soc_S_peripheral_50000000_S_uart_a000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_REG_IDX_0_VAL_ADDRESS 1342218240 /* 0x5000a000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_VAL_irq 10 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_COMPAT_MATCHES_nordic_nrf_uarte 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_COMPAT_MODEL_IDX_0 "nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible {"nordic,nrf-uarte"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_IDX_0 "nordic,nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_IDX_0 40960 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_IDX_0 10 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_hw_flow_control 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_disable_rx 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_disable_rx_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/uart@b000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_b000 * * Binding (compatible = nordic,nrf-uarte): * $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PATH "/soc/peripheral@50000000/uart@b000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FULL_NAME "uart@b000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_CHILD_IDX 18 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_ORD 95 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_ORD_STR_SORTABLE 00095 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_EXISTS 1 #define DT_N_INST_3_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_b000 #define DT_N_NODELABEL_uart3 DT_N_S_soc_S_peripheral_50000000_S_uart_b000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_irq 11 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MATCHES_nordic_nrf_uarte 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MODEL_IDX_0 "nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible {"nordic,nrf-uarte"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0 "nordic,nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_0 45056 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_0 11 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_hw_flow_control 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_disable_rx 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_disable_rx_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/vmc@3a000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000 * * Binding (compatible = nordic,nrf-vmc): * $ZEPHYR_BASE/dts/bindings/power/nordic,nrf-vmc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_PATH "/soc/peripheral@50000000/vmc@3a000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FULL_NAME "vmc@3a000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_CHILD_IDX 14 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_ORD 96 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_ORD_STR_SORTABLE 00096 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_REQUIRES_ORDS \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_vmc DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000 #define DT_N_NODELABEL_vmc DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_REG_IDX_0_VAL_ADDRESS 1342414848 /* 0x5003a000 */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_COMPAT_MATCHES_nordic_nrf_vmc 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_COMPAT_MODEL_IDX_0 "nrf-vmc" #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible {"nordic,nrf-vmc"} #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_IDX_0 "nordic,nrf-vmc" #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-vmc #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_vmc #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_VMC #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg {237568 /* 0x3a000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_IDX_0 237568 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/watchdog@18000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000 * * Binding (compatible = nordic,nrf-wdt): * $ZEPHYR_BASE/dts/bindings/watchdog/nordic,nrf-wdt.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PATH "/soc/peripheral@50000000/watchdog@18000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FULL_NAME "watchdog@18000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_CHILD_IDX 36 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_ORD 97 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_ORD_STR_SORTABLE 00097 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_EXISTS 1 #define DT_N_ALIAS_watchdog0 DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000 #define DT_N_INST_0_nordic_nrf_wdt DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000 #define DT_N_NODELABEL_wdt DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000 #define DT_N_NODELABEL_wdt0 DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_VAL_ADDRESS 1342275584 /* 0x50018000 */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq 24 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MATCHES_nordic_nrf_wdt 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MODEL_IDX_0 "nrf-wdt" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible {"nordic,nrf-wdt"} #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0 "nordic,nrf-wdt" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-wdt #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_wdt #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_WDT #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg {98304 /* 0x18000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_0 98304 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts {24 /* 0x18 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_0 24 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000 * * Binding (compatible = nordic,nrf91-flash-controller): * $ZEPHYR_BASE/dts/bindings/flash_controller/nordic,nrf91-flash-controller.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PATH "/soc/peripheral@50000000/flash-controller@39000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FULL_NAME "flash-controller@39000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_CHILD_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_ORD 98 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_ORD_STR_SORTABLE 00098 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REQUIRES_ORDS \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_SUPPORTS_ORDS \ 99, /* /soc/peripheral@50000000/flash-controller@39000/flash@0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_EXISTS 1 #define DT_N_INST_0_nordic_nrf91_flash_controller DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000 #define DT_N_NODELABEL_flash_controller DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_VAL_ADDRESS 1342410752 /* 0x50039000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MATCHES_nordic_nrf91_flash_controller 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MODEL_IDX_0 "nrf91-flash-controller" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible {"nordic,nrf91-flash-controller"} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0 "nordic,nrf91-flash-controller" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf91-flash-controller #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf91_flash_controller #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF91_FLASH_CONTROLLER #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_0 233472 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_partial_erase 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_partial_erase_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0 * * Binding (compatible = soc-nv-flash): * $ZEPHYR_BASE/dts/bindings/mtd/soc-nv-flash.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FULL_NAME "flash@0" /* Node parent (/soc/peripheral@50000000/flash-controller@39000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_CHILD_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_ORD 99 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_ORD_STR_SORTABLE 00099 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REQUIRES_ORDS \ 98, /* /soc/peripheral@50000000/flash-controller@39000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_SUPPORTS_ORDS \ 100, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_EXISTS 1 #define DT_N_INST_0_soc_nv_flash DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0 #define DT_N_NODELABEL_flash0 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_SIZE 1048576 /* 0x100000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_COMPAT_MATCHES_soc_nv_flash 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible {"soc-nv-flash"} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0 "soc-nv-flash" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_UNQUOTED soc-nv-flash #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_TOKEN soc_nv_flash #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_UPPER_TOKEN SOC_NV_FLASH #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg {0 /* 0x0 */, 1048576 /* 0x100000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1 1048576 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_erase_block_size 4096 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_erase_block_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_write_block_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_write_block_size_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions * * Binding (compatible = fixed-partitions): * $ZEPHYR_BASE/dts/bindings/mtd/fixed-partitions.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FULL_NAME "partitions" /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_NUM 6 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_NUM_STATUS_OKAY 6 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_ORD 100 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_ORD_STR_SORTABLE 00100 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_REQUIRES_ORDS \ 99, /* /soc/peripheral@50000000/flash-controller@39000/flash@0 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_SUPPORTS_ORDS \ 101, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0 */ \ 102, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000 */ \ 103, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000 */ \ 104, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@85000 */ \ 105, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c5000 */ \ 106, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@fa000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_EXISTS 1 #define DT_N_INST_0_fixed_partitions DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_REG_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_COMPAT_MATCHES_fixed_partitions 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FULL_NAME "partition@0" /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_ORD 101 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_ORD_STR_SORTABLE 00101 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REQUIRES_ORDS \ 100, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_EXISTS 1 #define DT_N_NODELABEL_boot_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARTITION_ID 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label "mcuboot" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UNQUOTED mcuboot #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_TOKEN mcuboot #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN MCUBOOT #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_IDX_0 "mcuboot" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 65536 /* 0x10000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1 65536 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME "partition@10000" /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_IDX 1 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_ORD 102 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_ORD_STR_SORTABLE 00102 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REQUIRES_ORDS \ 100, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_EXISTS 1 #define DT_N_NODELABEL_slot0_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_ADDRESS 65536 /* 0x10000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARTITION_ID 1 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label "image-0" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UNQUOTED image-0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_TOKEN image_0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UPPER_TOKEN IMAGE_0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_IDX_0 "image-0" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg {65536 /* 0x10000 */, 262144 /* 0x40000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0 65536 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1 262144 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FULL_NAME "partition@50000" /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_CHILD_IDX 2 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_ORD 103 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_ORD_STR_SORTABLE 00103 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REQUIRES_ORDS \ 100, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_EXISTS 1 #define DT_N_NODELABEL_slot0_ns_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_ADDRESS 327680 /* 0x50000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_SIZE 217088 /* 0x35000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARTITION_ID 2 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label "image-0-nonsecure" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_UNQUOTED image-0-nonsecure #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_TOKEN image_0_nonsecure #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_UPPER_TOKEN IMAGE_0_NONSECURE #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_IDX_0 "image-0-nonsecure" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg {327680 /* 0x50000 */, 217088 /* 0x35000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0 327680 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1 217088 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@85000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@85000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_FULL_NAME "partition@85000" /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_CHILD_IDX 3 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_ORD 104 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_ORD_STR_SORTABLE 00104 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_REQUIRES_ORDS \ 100, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_EXISTS 1 #define DT_N_NODELABEL_slot1_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_REG_IDX_0_VAL_ADDRESS 544768 /* 0x85000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_PARTITION_ID 3 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_label "image-1" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_label_STRING_UNQUOTED image-1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_label_STRING_TOKEN image_1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_label_STRING_UPPER_TOKEN IMAGE_1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_label_IDX_0 "image-1" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_reg {544768 /* 0x85000 */, 262144 /* 0x40000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_reg_IDX_0 544768 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_reg_IDX_1 262144 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c5000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c5000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_FULL_NAME "partition@c5000" /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_CHILD_IDX 4 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_ORD 105 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_ORD_STR_SORTABLE 00105 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_REQUIRES_ORDS \ 100, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_EXISTS 1 #define DT_N_NODELABEL_slot1_ns_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_REG_IDX_0_VAL_ADDRESS 806912 /* 0xc5000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_REG_IDX_0_VAL_SIZE 217088 /* 0x35000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_PARTITION_ID 4 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_label "image-1-nonsecure" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_label_STRING_UNQUOTED image-1-nonsecure #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_label_STRING_TOKEN image_1_nonsecure #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_label_STRING_UPPER_TOKEN IMAGE_1_NONSECURE #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_label_IDX_0 "image-1-nonsecure" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_reg {806912 /* 0xc5000 */, 217088 /* 0x35000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_reg_IDX_0 806912 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_reg_IDX_1 217088 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@fa000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@fa000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FULL_NAME "partition@fa000" /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_CHILD_IDX 5 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_ORD 106 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_ORD_STR_SORTABLE 00106 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REQUIRES_ORDS \ 100, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_EXISTS 1 #define DT_N_NODELABEL_storage_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_ADDRESS 1024000 /* 0xfa000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_SIZE 24576 /* 0x6000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARTITION_ID 5 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label "storage" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_STRING_UNQUOTED storage #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_STRING_TOKEN storage #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_STRING_UPPER_TOKEN STORAGE #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_IDX_0 "storage" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg {1024000 /* 0xfa000 */, 24576 /* 0x6000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0 1024000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1 24576 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2c@a000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_a000 * * Binding (compatible = nordic,nrf-twim): * $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PATH "/soc/peripheral@50000000/i2c@a000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FULL_NAME "i2c@a000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_CHILD_IDX 21 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_CHILD_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_ORD 107 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_ORD_STR_SORTABLE 00107 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ \ 28, /* /pin-controller/i2c2_default */ \ 30, /* /pin-controller/i2c2_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_SUPPORTS_ORDS \ 108, /* /soc/peripheral@50000000/i2c@a000/pcal6408a@21 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_a000 #define DT_N_NODELABEL_i2c2 DT_N_S_soc_S_peripheral_50000000_S_i2c_a000 #define DT_N_NODELABEL_arduino_i2c DT_N_S_soc_S_peripheral_50000000_S_i2c_a000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_REG_IDX_0_VAL_ADDRESS 1342218240 /* 0x5000a000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_VAL_irq 10 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_COMPAT_MATCHES_nordic_nrf_twim 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_COMPAT_MODEL_IDX_0 "nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_i2c2_default #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_i2c2_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible {"nordic,nrf-twim"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_IDX_0 "nordic,nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_IDX_0 40960 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_IDX_0 10 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_clock_frequency 400000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_clock_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_sq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_sq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_cq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_cq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_i2c2_default #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_i2c2_default #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_i2c2_sleep #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_i2c2_sleep #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_easydma_maxcnt_bits 13 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_zephyr_concat_buf_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_zephyr_concat_buf_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_zephyr_flash_buf_max_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_zephyr_flash_buf_max_size_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2c@a000/pcal6408a@21 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21 * * Binding (compatible = nxp,pcal6408a): * $ZEPHYR_BASE/dts/bindings/gpio/nxp,pcal6408a.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_PATH "/soc/peripheral@50000000/i2c@a000/pcal6408a@21" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_FULL_NAME "pcal6408a@21" /* Node parent (/soc/peripheral@50000000/i2c@a000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_PARENT DT_N_S_soc_S_peripheral_50000000_S_i2c_a000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_ORD 108 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_ORD_STR_SORTABLE 00108 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000/gpio@842500 */ \ 107, /* /soc/peripheral@50000000/i2c@a000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_EXISTS 1 #define DT_N_INST_0_nxp_pcal6408a DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21 #define DT_N_NODELABEL_pcal6408a DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21 /* Bus info (controller: '/soc/peripheral@50000000/i2c@a000', type: '['i2c']') */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_BUS_i2c 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_BUS DT_N_S_soc_S_peripheral_50000000_S_i2c_a000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_REG_IDX_0_VAL_ADDRESS 33 /* 0x21 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_COMPAT_MATCHES_nxp_pcal6408a 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_COMPAT_VENDOR_IDX_0 "NXP Semiconductors" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_COMPAT_MODEL_IDX_0 "pcal6408a" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_compatible {"nxp,pcal6408a"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_compatible_IDX_0 "nxp,pcal6408a" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_compatible_IDX_0_STRING_UNQUOTED nxp,pcal6408a #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_compatible_IDX_0_STRING_TOKEN nxp_pcal6408a #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_compatible_IDX_0_STRING_UPPER_TOKEN NXP_PCAL6408A #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_reg {33 /* 0x21 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_reg_IDX_0 33 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_gpio_controller 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_gpio_controller_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_ngpios 8 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_ngpios_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_int_gpios_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_int_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_int_gpios_IDX_0_VAL_pin 19 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_int_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_int_gpios_IDX_0_VAL_flags 17 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_int_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_int_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, int_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_int_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, int_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_int_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, int_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_int_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, int_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_int_gpios_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21_P_int_gpios_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/power@5000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000 * * Binding (compatible = nordic,nrf-power): * $ZEPHYR_BASE/dts/bindings/power/nordic,nrf-power.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PATH "/soc/peripheral@50000000/power@5000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FULL_NAME "power@5000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_CHILD_IDX 35 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_CHILD_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_CHILD_NUM_STATUS_OKAY 2 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_ORD 109 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_ORD_STR_SORTABLE 00109 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_SUPPORTS_ORDS \ 110, /* /soc/peripheral@50000000/power@5000/gpregret1@51c */ \ 111, /* /soc/peripheral@50000000/power@5000/gpregret2@520 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_power DT_N_S_soc_S_peripheral_50000000_S_power_5000 #define DT_N_NODELABEL_power DT_N_S_soc_S_peripheral_50000000_S_power_5000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 20480 /* 0x5000 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_IDX_0_VAL_LENGTH 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_irq 5 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MATCHES_nordic_nrf_power 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MODEL_IDX_0 "nrf-power" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible {"nordic,nrf-power"} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0 "nordic,nrf-power" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-power #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_power #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_POWER #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_0 20480 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_0 5 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/power@5000/gpregret1@51c * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c * * Binding (compatible = nordic,nrf-gpregret): * $ZEPHYR_BASE/dts/bindings/retained_mem/nordic,nrf-gpreget.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_PATH "/soc/peripheral@50000000/power@5000/gpregret1@51c" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FULL_NAME "gpregret1@51c" /* Node parent (/soc/peripheral@50000000/power@5000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_PARENT DT_N_S_soc_S_peripheral_50000000_S_power_5000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_ORD 110 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_ORD_STR_SORTABLE 00110 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REQUIRES_ORDS \ 109, /* /soc/peripheral@50000000/power@5000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_EXISTS 1 #define DT_N_INST_0_nordic_nrf_gpregret DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c #define DT_N_NODELABEL_gpregret1 DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REG_IDX_0_VAL_ADDRESS 1342199068 /* 0x5000551c */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REG_IDX_0_VAL_SIZE 1 /* 0x1 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_MATCHES_nordic_nrf_gpregret 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_MODEL_IDX_0 "nrf-gpregret" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible {"nordic,nrf-gpregret"} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0 "nordic,nrf-gpregret" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpregret #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpregret #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPREGRET #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg {1308 /* 0x51c */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_IDX_0 1308 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/power@5000/gpregret2@520 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520 * * Binding (compatible = nordic,nrf-gpregret): * $ZEPHYR_BASE/dts/bindings/retained_mem/nordic,nrf-gpreget.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_PATH "/soc/peripheral@50000000/power@5000/gpregret2@520" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FULL_NAME "gpregret2@520" /* Node parent (/soc/peripheral@50000000/power@5000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_PARENT DT_N_S_soc_S_peripheral_50000000_S_power_5000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_CHILD_IDX 1 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_ORD 111 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_ORD_STR_SORTABLE 00111 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REQUIRES_ORDS \ 109, /* /soc/peripheral@50000000/power@5000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_EXISTS 1 #define DT_N_INST_1_nordic_nrf_gpregret DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520 #define DT_N_NODELABEL_gpregret2 DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REG_IDX_0_VAL_ADDRESS 1342199072 /* 0x50005520 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REG_IDX_0_VAL_SIZE 1 /* 0x1 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_MATCHES_nordic_nrf_gpregret 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_MODEL_IDX_0 "nrf-gpregret" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible {"nordic,nrf-gpregret"} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0 "nordic,nrf-gpregret" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpregret #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpregret #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPREGRET #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg {1312 /* 0x520 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_IDX_0 1312 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_zephyr_deferred_init_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/spi@b000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_b000 * * Binding (compatible = nordic,nrf-spim): * $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PATH "/soc/peripheral@50000000/spi@b000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FULL_NAME "spi@b000" /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_CHILD_IDX 26 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_CHILD_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_ORD 112 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_ORD_STR_SORTABLE 00112 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REQUIRES_ORDS \ 7, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/peripheral@50000000 */ \ 10, /* /soc/peripheral@50000000/gpio@842500 */ \ 36, /* /pin-controller/spi3_default */ \ 38, /* /pin-controller/spi3_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_SUPPORTS_ORDS \ 113, /* /soc/peripheral@50000000/spi@b000/gd25wb256e3ir@1 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_b000 #define DT_N_NODELABEL_spi3 DT_N_S_soc_S_peripheral_50000000_S_spi_b000 #define DT_N_NODELABEL_arduino_spi DT_N_S_soc_S_peripheral_50000000_S_spi_b000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_irq 11 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MATCHES_nordic_nrf_spim 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MODEL_IDX_0 "nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spi3_default #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_spi3_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible {"nordic,nrf-spim"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0 "nordic,nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_0 45056 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_0 11 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_0_VAL_pin 10 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_0_VAL_flags 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_1_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_1_VAL_pin 20 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_1_VAL_pin_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_1_VAL_flags 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_1_VAL_flags_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, cs_gpios, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, cs_gpios, 1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, cs_gpios, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, cs_gpios, 1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, cs_gpios, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, cs_gpios, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, cs_gpios, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, cs_gpios, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spi3_default #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spi3_default #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_spi3_sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_spi3_sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_max_frequency 8000000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_overrun_character 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_overrun_character_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_easydma_maxcnt_bits 13 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_anomaly_58_workaround 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_anomaly_58_workaround_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_rx_delay_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_rx_delay_supported_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/spi@b000/gd25wb256e3ir@1 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1 * * Binding (compatible = jedec,spi-nor): * $ZEPHYR_BASE/dts/bindings/mtd/jedec,spi-nor.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_PATH "/soc/peripheral@50000000/spi@b000/gd25wb256e3ir@1" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_FULL_NAME "gd25wb256e3ir@1" /* Node parent (/soc/peripheral@50000000/spi@b000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_PARENT DT_N_S_soc_S_peripheral_50000000_S_spi_b000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_CHILD_IDX 0 /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_ORD 113 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_ORD_STR_SORTABLE 00113 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_REQUIRES_ORDS \ 112, /* /soc/peripheral@50000000/spi@b000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_EXISTS 1 #define DT_N_ALIAS_spi_flash0 DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1 #define DT_N_INST_0_jedec_spi_nor DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1 #define DT_N_NODELABEL_gd25wb256 DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1 /* Bus info (controller: '/soc/peripheral@50000000/spi@b000', type: '['spi']') */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_BUS_spi 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_BUS DT_N_S_soc_S_peripheral_50000000_S_spi_b000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_REG_IDX_0_VAL_ADDRESS 1 /* 0x1 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_COMPAT_MATCHES_jedec_spi_nor 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_COMPAT_VENDOR_IDX_0 "JEDEC Solid State Technology Association" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_COMPAT_MODEL_IDX_0 "spi-nor" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_ENUM_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_ENUM_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_compatible {"jedec,spi-nor"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_compatible_IDX_0 "jedec,spi-nor" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_compatible_IDX_0_STRING_UNQUOTED jedec,spi-nor #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_compatible_IDX_0_STRING_TOKEN jedec_spi_nor #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_compatible_IDX_0_STRING_UPPER_TOKEN JEDEC_SPI_NOR #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_reg {1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_reg_IDX_0 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_spi_max_frequency 8000000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_spi_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_duplex 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_duplex_ENUM_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_duplex_ENUM_VAL_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_duplex_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_frame_format 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_frame_format_ENUM_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_frame_format_ENUM_VAL_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_frame_format_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_spi_cpol 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_spi_cpol_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_spi_cpha 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_spi_cpha_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_spi_hold_cs 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_spi_hold_cs_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id {200 /* 0xc8 */, 101 /* 0x65 */, 25 /* 0x19 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id_IDX_0 200 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id_IDX_1 101 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id_IDX_2 25 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id_IDX_2_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, jedec_id, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, jedec_id, 1) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, jedec_id, 2) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, jedec_id, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, jedec_id, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, jedec_id, 2) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, jedec_id, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, jedec_id, 1, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, jedec_id, 2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, jedec_id, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, jedec_id, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, jedec_id, 2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id_LEN 3 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_jedec_id_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_size 268435456 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp {229 /* 0xe5 */, 32 /* 0x20 */, 243 /* 0xf3 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 15 /* 0xf */, 68 /* 0x44 */, 235 /* 0xeb */, 8 /* 0x8 */, 107 /* 0x6b */, 8 /* 0x8 */, 59 /* 0x3b */, 66 /* 0x42 */, 187 /* 0xbb */, 238 /* 0xee */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 12 /* 0xc */, 32 /* 0x20 */, 15 /* 0xf */, 82 /* 0x52 */, 16 /* 0x10 */, 216 /* 0xd8 */, 0 /* 0x0 */, 255 /* 0xff */, 68 /* 0x44 */, 122 /* 0x7a */, 201 /* 0xc9 */, 254 /* 0xfe */, 131 /* 0x83 */, 103 /* 0x67 */, 38 /* 0x26 */, 98 /* 0x62 */, 236 /* 0xec */, 130 /* 0x82 */, 24 /* 0x18 */, 68 /* 0x44 */, 122 /* 0x7a */, 117 /* 0x75 */, 122 /* 0x7a */, 117 /* 0x75 */, 4 /* 0x4 */, 196 /* 0xc4 */, 213 /* 0xd5 */, 92 /* 0x5c */, 0 /* 0x0 */, 6 /* 0x6 */, 116 /* 0x74 */, 0 /* 0x0 */, 8 /* 0x8 */, 80 /* 0x50 */, 0 /* 0x0 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_0 229 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_1 32 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_2 243 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_2_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_3 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_3_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_4 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_4_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_5 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_5_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_6 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_6_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_7 15 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_7_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_8 68 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_8_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_9 235 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_9_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_10 8 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_10_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_11 107 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_11_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_12 8 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_12_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_13 59 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_13_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_14 66 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_14_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_15 187 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_15_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_16 238 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_16_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_17 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_17_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_18 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_18_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_19 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_19_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_20 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_20_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_21 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_21_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_22 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_22_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_23 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_23_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_24 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_24_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_25 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_25_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_26 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_26_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_27 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_27_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_28 12 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_28_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_29 32 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_29_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_30 15 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_30_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_31 82 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_31_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_32 16 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_32_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_33 216 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_33_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_34 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_34_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_35 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_35_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_36 68 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_36_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_37 122 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_37_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_38 201 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_38_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_39 254 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_39_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_40 131 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_40_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_41 103 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_41_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_42 38 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_42_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_43 98 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_43_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_44 236 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_44_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_45 130 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_45_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_46 24 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_46_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_47 68 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_47_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_48 122 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_48_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_49 117 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_49_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_50 122 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_50_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_51 117 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_51_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_52 4 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_52_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_53 196 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_53_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_54 213 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_54_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_55 92 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_55_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_56 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_56_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_57 6 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_57_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_58 116 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_58_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_59 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_59_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_60 8 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_60_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_61 80 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_61_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_62 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_62_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_63 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_IDX_63_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 1) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 2) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 3) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 4) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 5) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 6) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 7) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 8) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 9) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 10) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 11) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 12) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 13) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 14) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 15) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 16) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 17) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 18) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 19) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 20) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 21) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 22) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 23) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 24) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 25) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 26) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 27) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 28) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 29) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 30) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 31) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 32) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 33) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 34) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 35) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 36) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 37) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 38) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 39) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 40) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 41) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 42) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 43) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 44) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 45) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 46) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 47) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 48) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 49) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 50) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 51) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 52) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 53) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 54) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 55) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 56) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 57) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 58) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 59) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 60) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 61) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 62) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 63) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 3) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 4) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 5) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 6) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 7) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 8) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 9) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 10) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 11) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 12) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 13) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 14) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 15) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 16) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 17) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 18) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 19) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 20) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 21) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 22) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 23) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 24) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 25) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 26) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 27) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 28) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 29) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 30) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 31) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 32) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 33) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 34) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 35) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 36) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 37) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 38) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 39) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 40) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 41) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 42) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 43) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 44) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 45) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 46) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 47) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 48) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 49) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 50) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 51) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 52) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 53) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 54) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 55) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 56) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 57) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 58) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 59) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 60) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 61) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 62) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 63) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 1, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 2, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 3, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 4, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 5, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 6, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 7, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 8, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 9, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 10, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 11, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 12, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 13, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 14, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 15, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 16, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 17, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 18, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 19, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 20, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 21, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 22, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 23, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 24, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 25, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 26, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 27, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 28, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 29, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 30, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 31, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 32, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 33, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 34, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 35, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 36, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 37, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 38, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 39, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 40, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 41, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 42, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 43, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 44, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 45, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 46, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 47, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 48, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 49, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 50, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 51, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 52, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 53, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 54, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 55, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 56, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 57, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 58, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 59, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 60, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 61, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 62, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 63, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 17, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 18, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 19, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 20, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 21, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 22, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 23, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 24, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 25, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 26, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 27, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 28, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 29, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 30, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 31, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 32, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 33, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 34, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 35, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 36, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 37, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 38, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 39, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 40, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 41, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 42, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 43, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 44, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 45, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 46, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 47, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 48, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 49, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 50, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 51, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 52, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 53, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 54, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 55, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 56, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 57, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 58, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 59, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 60, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 61, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 62, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, sfdp_bfp, 63, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_LEN 64 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_sfdp_bfp_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_requires_ulbpr 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_requires_ulbpr_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_has_dpd 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_has_dpd_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_t_enter_dpd 3000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_t_enter_dpd_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_t_exit_dpd 40000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1_P_t_exit_dpd_EXISTS 1 /* * Chosen nodes */ #define DT_CHOSEN_zephyr_entropy DT_N_S_soc_S_crypto_50840000 #define DT_CHOSEN_zephyr_entropy_EXISTS 1 #define DT_CHOSEN_zephyr_flash_controller DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000 #define DT_CHOSEN_zephyr_flash_controller_EXISTS 1 #define DT_CHOSEN_zephyr_console DT_N_S_soc_S_peripheral_50000000_S_uart_8000 #define DT_CHOSEN_zephyr_console_EXISTS 1 #define DT_CHOSEN_zephyr_shell_uart DT_N_S_soc_S_peripheral_50000000_S_uart_8000 #define DT_CHOSEN_zephyr_shell_uart_EXISTS 1 #define DT_CHOSEN_zephyr_uart_mcumgr DT_N_S_soc_S_peripheral_50000000_S_uart_8000 #define DT_CHOSEN_zephyr_uart_mcumgr_EXISTS 1 #define DT_CHOSEN_zephyr_sram DT_N_S_reserved_memory_S_image_s_20000000 #define DT_CHOSEN_zephyr_sram_EXISTS 1 #define DT_CHOSEN_zephyr_flash DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0 #define DT_CHOSEN_zephyr_flash_EXISTS 1 #define DT_CHOSEN_zephyr_code_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0 #define DT_CHOSEN_zephyr_code_partition_EXISTS 1 #define DT_CHOSEN_zephyr_sram_secure_partition DT_N_S_reserved_memory_S_image_s_20000000 #define DT_CHOSEN_zephyr_sram_secure_partition_EXISTS 1 #define DT_CHOSEN_zephyr_sram_non_secure_partition DT_N_S_reserved_memory_S_image_ns_20020000 #define DT_CHOSEN_zephyr_sram_non_secure_partition_EXISTS 1 /* Macros for iterating over all nodes and enabled nodes */ #define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) fn(DT_N_S_soc_S_crypto_50840000) fn(DT_N_S_soc_S_ctrlap_50006000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_gpiote_40031000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) fn(DT_N_S_pin_controller_S_i2c2_default) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1) fn(DT_N_S_pin_controller_S_i2c2_sleep) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm0_default) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi3_default) fn(DT_N_S_pin_controller_S_spi3_default_S_group1) fn(DT_N_S_pin_controller_S_spi3_sleep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_sw_pwm) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_pwmleds) fn(DT_N_S_pwmleds_S_pwm_led_0) fn(DT_N_S_buttons) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) fn(DT_N_S_gpio_reset) fn(DT_N_S_connector) fn(DT_N_S_analog_connector) fn(DT_N_S_reserved_memory) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_modem_20016000) fn(DT_N_S_reserved_memory_S_image_ns_20020000) #define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_crypto_50840000) fn(DT_N_S_soc_S_ctrlap_50006000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) fn(DT_N_S_pin_controller_S_i2c2_default) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1) fn(DT_N_S_pin_controller_S_i2c2_sleep) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm0_default) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi3_default) fn(DT_N_S_pin_controller_S_spi3_default_S_group1) fn(DT_N_S_pin_controller_S_spi3_sleep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_pwmleds) fn(DT_N_S_pwmleds_S_pwm_led_0) fn(DT_N_S_buttons) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) fn(DT_N_S_connector) fn(DT_N_S_analog_connector) fn(DT_N_S_reserved_memory) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_modem_20016000) fn(DT_N_S_reserved_memory_S_image_ns_20020000) #define DT_FOREACH_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_S_pcal6408a_21, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_gd25wb256e3ir_1, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__) fn(DT_N_S_soc_S_ctrlap_50006000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_40031000, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_sw_pwm, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) fn(DT_N_S_gpio_reset, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_analog_connector, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__) #define DT_FOREACH_OKAY_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__) fn(DT_N_S_soc_S_ctrlap_50006000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_analog_connector, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__) #define DT_COMPAT_fixed_partitions_LABEL_mcuboot DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0 #define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_image_0 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000 #define DT_COMPAT_fixed_partitions_LABEL_image_0_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000 #define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_image_1 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_85000 #define DT_COMPAT_fixed_partitions_LABEL_image_1_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c5000 #define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_storage DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000 #define DT_COMPAT_fixed_partitions_LABEL_storage_EXISTS 1 /* * Macros for compatibles with status "okay" nodes */ #define DT_COMPAT_HAS_OKAY_nordic_nrf9161_dk_nrf9161 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf9161_laca 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf9120 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf91 1 #define DT_COMPAT_HAS_OKAY_simple_bus 1 #define DT_COMPAT_HAS_OKAY_arm_v8m_nvic 1 #define DT_COMPAT_HAS_OKAY_mmio_sram 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf91_flash_controller 1 #define DT_COMPAT_HAS_OKAY_soc_nv_flash 1 #define DT_COMPAT_HAS_OKAY_fixed_partitions 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_saadc 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_dppic 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_egu 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_ipc 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_kmu 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_regulators 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_vmc 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_uarte 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_twim 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_spim 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_pwm 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_clock 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_power 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_gpregret 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_wdt 1 #define DT_COMPAT_HAS_OKAY_nordic_cryptocell 1 #define DT_COMPAT_HAS_OKAY_arm_cryptocell_310 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_ctrlapperi 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_spu 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_ficr 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_uicr 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_pinctrl 1 #define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_entropy 1 #define DT_COMPAT_HAS_OKAY_arm_cortex_m33f 1 #define DT_COMPAT_HAS_OKAY_arm_armv8m_mpu 1 #define DT_COMPAT_HAS_OKAY_gpio_leds 1 #define DT_COMPAT_HAS_OKAY_pwm_leds 1 #define DT_COMPAT_HAS_OKAY_gpio_keys 1 #define DT_COMPAT_HAS_OKAY_arduino_header_r3 1 #define DT_COMPAT_HAS_OKAY_arduino_uno_adc 1 /* * Macros for status "okay" instances of each compatible */ #define DT_N_INST_nordic_nrf9161_dk_nrf9161_NUM_OKAY 1 #define DT_N_INST_nordic_nrf9161_laca_NUM_OKAY 1 #define DT_N_INST_nordic_nrf9120_NUM_OKAY 1 #define DT_N_INST_nordic_nrf91_NUM_OKAY 1 #define DT_N_INST_simple_bus_NUM_OKAY 1 #define DT_N_INST_arm_v8m_nvic_NUM_OKAY 1 #define DT_N_INST_mmio_sram_NUM_OKAY 1 #define DT_N_INST_nordic_nrf91_flash_controller_NUM_OKAY 1 #define DT_N_INST_soc_nv_flash_NUM_OKAY 1 #define DT_N_INST_fixed_partitions_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_saadc_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_dppic_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_egu_NUM_OKAY 6 #define DT_N_INST_nordic_nrf_ipc_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_kmu_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_regulators_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_vmc_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_uarte_NUM_OKAY 2 #define DT_N_INST_nordic_nrf_twim_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_spim_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_pwm_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_gpio_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_clock_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_power_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_gpregret_NUM_OKAY 2 #define DT_N_INST_nordic_nrf_wdt_NUM_OKAY 1 #define DT_N_INST_nordic_cryptocell_NUM_OKAY 1 #define DT_N_INST_arm_cryptocell_310_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_ctrlapperi_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_gpiote_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_spu_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_ficr_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_uicr_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_pinctrl_NUM_OKAY 1 #define DT_N_INST_zephyr_bt_hci_entropy_NUM_OKAY 1 #define DT_N_INST_arm_cortex_m33f_NUM_OKAY 1 #define DT_N_INST_arm_armv8m_mpu_NUM_OKAY 1 #define DT_N_INST_gpio_leds_NUM_OKAY 1 #define DT_N_INST_pwm_leds_NUM_OKAY 1 #define DT_N_INST_gpio_keys_NUM_OKAY 1 #define DT_N_INST_arduino_header_r3_NUM_OKAY 1 #define DT_N_INST_arduino_uno_adc_NUM_OKAY 1 #define DT_FOREACH_OKAY_nordic_nrf9161_dk_nrf9161(fn) fn(DT_N) #define DT_FOREACH_OKAY_VARGS_nordic_nrf9161_dk_nrf9161(fn, ...) fn(DT_N, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf9161_dk_nrf9161(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf9161_dk_nrf9161(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf9161_laca(fn) fn(DT_N_S_soc) #define DT_FOREACH_OKAY_VARGS_nordic_nrf9161_laca(fn, ...) fn(DT_N_S_soc, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf9161_laca(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf9161_laca(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf9120(fn) fn(DT_N_S_soc) #define DT_FOREACH_OKAY_VARGS_nordic_nrf9120(fn, ...) fn(DT_N_S_soc, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf9120(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf9120(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf91(fn) fn(DT_N_S_soc) #define DT_FOREACH_OKAY_VARGS_nordic_nrf91(fn, ...) fn(DT_N_S_soc, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf91(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf91(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_simple_bus(fn) fn(DT_N_S_soc) #define DT_FOREACH_OKAY_VARGS_simple_bus(fn, ...) fn(DT_N_S_soc, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_simple_bus(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_arm_v8m_nvic(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) #define DT_FOREACH_OKAY_VARGS_arm_v8m_nvic(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_arm_v8m_nvic(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_arm_v8m_nvic(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_mmio_sram(fn) fn(DT_N_S_soc_S_memory_20000000) #define DT_FOREACH_OKAY_VARGS_mmio_sram(fn, ...) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_mmio_sram(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf91_flash_controller(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf91_flash_controller(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf91_flash_controller(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf91_flash_controller(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_soc_nv_flash(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) #define DT_FOREACH_OKAY_VARGS_soc_nv_flash(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_fixed_partitions(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) #define DT_FOREACH_OKAY_VARGS_fixed_partitions(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_fixed_partitions(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_fixed_partitions(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_saadc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_saadc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_saadc(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_saadc(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_dppic(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_dppic(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_dppic(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_dppic(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_egu(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_egu(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_egu(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_egu(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_ipc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_ipc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_ipc(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ipc(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_kmu(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_kmu(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_kmu(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_kmu(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_regulators(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_regulators(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_regulators(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_regulators(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_vmc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_vmc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_vmc(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_vmc(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_uarte(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_uarte(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_uarte(fn) fn(0) fn(1) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uarte(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_twim(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_twim(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_twim(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_twim(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_spim(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_spim(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_spim(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spim(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_pwm(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_pwm(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_pwm(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pwm(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_gpio(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpio(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_gpio(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpio(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_clock(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_clock(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_clock(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_clock(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_power(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_power(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_power(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_power(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_gpregret(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpregret(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_gpregret(fn) fn(0) fn(1) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpregret(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_wdt(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_wdt(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_wdt(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_wdt(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_cryptocell(fn) fn(DT_N_S_soc_S_crypto_50840000) #define DT_FOREACH_OKAY_VARGS_nordic_cryptocell(fn, ...) fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_cryptocell(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_cryptocell(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_arm_cryptocell_310(fn) fn(DT_N_S_soc_S_crypto_50840000) #define DT_FOREACH_OKAY_VARGS_arm_cryptocell_310(fn, ...) fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_arm_cryptocell_310(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_arm_cryptocell_310(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_ctrlapperi(fn) fn(DT_N_S_soc_S_ctrlap_50006000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_ctrlapperi(fn, ...) fn(DT_N_S_soc_S_ctrlap_50006000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_ctrlapperi(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ctrlapperi(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_gpiote(fn) fn(DT_N_S_soc_S_gpiote_5000d000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpiote(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_gpiote(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpiote(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_spu(fn) fn(DT_N_S_soc_S_spu_50003000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_spu(fn, ...) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_spu(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spu(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_ficr(fn) fn(DT_N_S_soc_S_ficr_ff0000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_ficr(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_ficr(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ficr(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_uicr(fn) fn(DT_N_S_soc_S_uicr_ff8000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_uicr(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_uicr(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uicr(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_pinctrl(fn) fn(DT_N_S_pin_controller) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_pinctrl(fn, ...) fn(DT_N_S_pin_controller, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_pinctrl(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pinctrl(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_zephyr_bt_hci_entropy(fn) fn(DT_N_S_entropy_bt_hci) #define DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_zephyr_bt_hci_entropy(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_arm_cortex_m33f(fn) fn(DT_N_S_cpus_S_cpu_0) #define DT_FOREACH_OKAY_VARGS_arm_cortex_m33f(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_arm_cortex_m33f(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_arm_cortex_m33f(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_arm_armv8m_mpu(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) #define DT_FOREACH_OKAY_VARGS_arm_armv8m_mpu(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_arm_armv8m_mpu(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_arm_armv8m_mpu(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_gpio_leds(fn) fn(DT_N_S_leds) #define DT_FOREACH_OKAY_VARGS_gpio_leds(fn, ...) fn(DT_N_S_leds, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_gpio_leds(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_gpio_leds(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_pwm_leds(fn) fn(DT_N_S_pwmleds) #define DT_FOREACH_OKAY_VARGS_pwm_leds(fn, ...) fn(DT_N_S_pwmleds, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_pwm_leds(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_pwm_leds(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_gpio_keys(fn) fn(DT_N_S_buttons) #define DT_FOREACH_OKAY_VARGS_gpio_keys(fn, ...) fn(DT_N_S_buttons, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_gpio_keys(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_gpio_keys(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_arduino_header_r3(fn) fn(DT_N_S_connector) #define DT_FOREACH_OKAY_VARGS_arduino_header_r3(fn, ...) fn(DT_N_S_connector, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_arduino_header_r3(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_arduino_header_r3(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_arduino_uno_adc(fn) fn(DT_N_S_analog_connector) #define DT_FOREACH_OKAY_VARGS_arduino_uno_adc(fn, ...) fn(DT_N_S_analog_connector, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_arduino_uno_adc(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_arduino_uno_adc(fn, ...) fn(0, __VA_ARGS__) /* * Bus information for status "okay" nodes of each compatible */