diff options
| author | Michal Hanus <mikehanus@protonmail.com> | 2025-04-14 22:04:32 +0200 |
|---|---|---|
| committer | Michal Hanus <mikehanus@protonmail.com> | 2025-04-14 22:04:32 +0200 |
| commit | 2e13c372f1419f08dab7797b244681f889dd9bcf (patch) | |
| tree | 995a31c40f13068c4135c213e938e0a2a9ed05a3 /nrfdemo/build/tfm/api_ns/platform/common | |
| parent | 620dfd94019f3c7e3022fa5a5fb9c9b51491062d (diff) | |
nrfdemo
Diffstat (limited to 'nrfdemo/build/tfm/api_ns/platform/common')
49 files changed, 6830 insertions, 0 deletions
diff --git a/nrfdemo/build/tfm/api_ns/platform/common/assert.c b/nrfdemo/build/tfm/api_ns/platform/common/assert.c new file mode 100644 index 0000000..2a2dacf --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/assert.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include <pm_config.h> +#include "autoconf.h" +#include "region_defs.h" +#include "utilities.h" + +#define IS_ALIGNED_POW2(value, align) (((value) & ((align)-1)) == 0) + +/* Making sure the borders between secure and non-secure regions are + * aligned with the SPU regions + */ +#if !(IS_ALIGNED_POW2(PM_TFM_NONSECURE_ADDRESS, CONFIG_NRF_SPU_FLASH_REGION_ALIGNMENT)) +#pragma message \ + "\n\n!!!Partition alignment error!!!" \ + "\nThe non-secure start address in pm_static.yml" \ + " or generated partition.yml is: " \ + M2S(PM_TFM_NONSECURE_ADDRESS) \ + "\nwhich is not aligned with the SPU HW requirements." \ + "\nRefer to the documentation section 'TF-M partition alignment requirements'" \ + "\nfor more information.\n\n" + +#error "TF-M non-secure start address is not aligned to SPU HW requirements" +#endif + +#if !(IS_ALIGNED_POW2(PM_SRAM_NONSECURE_ADDRESS, CONFIG_NRF_SPU_RAM_REGION_ALIGNMENT)) +#error "SRAM non-secure address is not aligned to SPU HW requirements" +#endif diff --git a/nrfdemo/build/tfm/api_ns/platform/common/attest_hal.c b/nrfdemo/build/tfm/api_ns/platform/common/attest_hal.c new file mode 100644 index 0000000..4fe9c93 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/attest_hal.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2018-2021, Arm Limited. All rights reserved. + * Copyright (c) 2022 Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + * + */ + +#include <stddef.h> +#include <stdint.h> +#include "tfm_attest_hal.h" +#include "tfm_plat_boot_seed.h" +#include "tfm_plat_device_id.h" +#include "tfm_plat_otp.h" +#include <nrf_cc3xx_platform.h> +#include "tfm_strnlen.h" +#include "nrf_provisioning.h" +#include <nrfx_nvmc.h> +#include <bl_storage.h> + +static enum tfm_security_lifecycle_t map_bl_storage_lcs_to_tfm_slc(enum lcs lcs) +{ + switch (lcs) { + case BL_STORAGE_LCS_ASSEMBLY: + return TFM_SLC_ASSEMBLY_AND_TEST; + case BL_STORAGE_LCS_PROVISIONING: + return TFM_SLC_PSA_ROT_PROVISIONING; + case BL_STORAGE_LCS_SECURED: + return TFM_SLC_SECURED; + case BL_STORAGE_LCS_DECOMMISSIONED: + return TFM_SLC_DECOMMISSIONED; + default: + return TFM_SLC_UNKNOWN; + } +} + +static enum lcs map_tfm_slc_to_bl_storage_lcs(enum tfm_security_lifecycle_t lcs) +{ + switch (lcs) { + case TFM_SLC_ASSEMBLY_AND_TEST: + return BL_STORAGE_LCS_ASSEMBLY; + case TFM_SLC_PSA_ROT_PROVISIONING: + return BL_STORAGE_LCS_PROVISIONING; + case TFM_SLC_SECURED: + return BL_STORAGE_LCS_SECURED; + case TFM_SLC_DECOMMISSIONED: + return BL_STORAGE_LCS_DECOMMISSIONED; + default: + return BL_STORAGE_LCS_UNKNOWN; + } +} + +enum tfm_security_lifecycle_t tfm_attest_hal_get_security_lifecycle(void) +{ + int err; + enum lcs otp_lcs; + + err = read_life_cycle_state(&otp_lcs); + if (err != 0) { + return TFM_SLC_UNKNOWN; + } + + return map_bl_storage_lcs_to_tfm_slc(otp_lcs); +} + +int tfm_attest_update_security_lifecycle_otp(enum tfm_security_lifecycle_t slc) +{ + enum lcs next_lcs; + + next_lcs = map_tfm_slc_to_bl_storage_lcs(slc); + + return update_life_cycle_state(next_lcs); +} + +enum tfm_plat_err_t tfm_attest_hal_get_verification_service(uint32_t *size, uint8_t *buf) +{ + enum tfm_plat_err_t err; + size_t otp_size; + size_t copy_size; + + err = tfm_plat_otp_read(PLAT_OTP_ID_VERIFICATION_SERVICE_URL, *size, buf); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + err = tfm_plat_otp_get_size(PLAT_OTP_ID_VERIFICATION_SERVICE_URL, &otp_size); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + /* Actually copied data is always the smaller */ + copy_size = *size < otp_size ? *size : otp_size; + /* String content */ + *size = tfm_strnlen((char *)buf, copy_size); + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_attest_hal_get_profile_definition(uint32_t *size, uint8_t *buf) +{ + enum tfm_plat_err_t err; + size_t otp_size; + size_t copy_size; + + err = tfm_plat_otp_read(PLAT_OTP_ID_PROFILE_DEFINITION, *size, buf); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + err = tfm_plat_otp_get_size(PLAT_OTP_ID_PROFILE_DEFINITION, &otp_size); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + /* Actually copied data is always the smaller */ + copy_size = *size < otp_size ? *size : otp_size; + /* String content */ + *size = tfm_strnlen((char *)buf, copy_size); + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_get_boot_seed(uint32_t size, uint8_t *buf) +{ + int nrf_err; + + if (size != NRF_CC3XX_PLATFORM_TFM_BOOT_SEED_SIZE) { + return TFM_PLAT_ERR_INVALID_INPUT; + } + + nrf_err = nrf_cc3xx_platform_get_boot_seed(buf); + if (nrf_err != NRF_CC3XX_PLATFORM_SUCCESS) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_get_implementation_id(uint32_t *size, uint8_t *buf) +{ + *size = BL_STORAGE_IMPLEMENTATION_ID_SIZE; + read_implementation_id_from_otp(buf); + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_get_cert_ref(uint32_t *size, uint8_t *buf) + +{ + enum tfm_plat_err_t err; + size_t otp_size; + size_t copy_size; + + err = tfm_plat_otp_read(PLAT_OTP_ID_CERT_REF, *size, buf); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + err = tfm_plat_otp_get_size(PLAT_OTP_ID_CERT_REF, &otp_size); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + /* Actually copied data is always the smaller */ + copy_size = *size < otp_size ? *size : otp_size; + /* String content */ + *size = tfm_strnlen((char *)buf, copy_size); + + return TFM_PLAT_ERR_SUCCESS; +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/config.cmake b/nrfdemo/build/tfm/api_ns/platform/common/config.cmake new file mode 100644 index 0000000..1265256 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/config.cmake @@ -0,0 +1,31 @@ +# +# Copyright (c) 2021 - 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# + +# Override the platform crypto key handling +set(PLATFORM_DEFAULT_CRYPTO_KEYS FALSE CACHE BOOL "Use default crypto keys implementation.") + +set(PLATFORM_DEFAULT_SYSTEM_RESET_HALT OFF CACHE BOOL "Use default system reset/halt implementation") + +# Disable crypto regression tests that are not supported +set(TFM_CRYPTO_TEST_ALG_CFB OFF CACHE BOOL "Test CFB cryptography mode") +set(TFM_CRYPTO_TEST_ALG_OFB OFF CACHE BOOL "Test OFB cryptography mode") + +# Always enable the nonsecure storage partition. +# It will still be excluded if the partition manager excludes it. +set(NRF_NS_STORAGE ON CACHE BOOL "Enable non-secure storage partition") +set(PLATFORM_DEFAULT_ATTEST_HAL OFF CACHE BOOL "Use default attest hal implementation.") + +set(NRF_ALLOW_NON_SECURE_RESET OFF CACHE BOOL "Allow system reset calls from Non-Secure") +set(NRF_ALLOW_NON_SECURE_FAULT_HANDLING OFF CACHE BOOL "Allow Non-Secure to handle Secure faults triggered by Non-Secure") + +set(TFM_DUMMY_PROVISIONING OFF CACHE BOOL "Provision with dummy values. NOT to be used in production") +set(PLATFORM_DEFAULT_PROVISIONING OFF CACHE BOOL "Use default provisioning implementation") +set(NRF_PROVISIONING OFF CACHE BOOL "Use Nordic provisioning implementation") +set(CONFIG_NFCT_PINS_AS_GPIOS OFF CACHE BOOL "Use NFCT pins as GPIOs.") +set(CONFIG_NRF_TRACE_PORT OFF CACHE BOOL "Enable trace port.") + +set(CONFIG_HW_UNIQUE_KEY ON CACHE BOOL "Enable Hardware Unique Key") +set(CONFIG_HW_UNIQUE_KEY_RANDOM ON CACHE BOOL "Write a new Hardware Unique Key if none exists") diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/CMakeLists.txt b/nrfdemo/build/tfm/api_ns/platform/common/core/CMakeLists.txt new file mode 100644 index 0000000..f2909da --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/CMakeLists.txt @@ -0,0 +1,69 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# This file is exported to NS side during CMake installation phase and renamed +# to CMakeLists.txt. It instructs how to build a platform on non-secture side. +# The structure and sources list are fully platform specific. + +target_compile_definitions(platform_region_defs + INTERFACE + $<$<BOOL:${NULL_POINTER_EXCEPTION_DETECTION}>:NULL_POINTER_EXCEPTION_DETECTION> + $<$<BOOL:${NRF_NS_STORAGE}>:NRF_NS_STORAGE> + $<$<BOOL:${NRF_NS_SECONDARY}>:NRF_NS_SECONDARY> +) + +# Startup sources should be put in the executable +target_sources(tfm_ns + PRIVATE + startup.c + $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/startup_${target}.c> +) + +# Additional NS API sources +target_sources(tfm_api_ns + PRIVATE + $<$<BOOL:${TFM_PARTITION_PLATFORM}>:${CONFIG_SPE_PATH}/interface/src/tfm_ioctl_core_ns_api.c> +) + +target_sources(platform_ns + PRIVATE + cmsis_drivers/Driver_USART.c + ${HAL_NORDIC_PATH}/nrfx/drivers/src/nrfx_uarte.c + nrfx_glue.c + $<$<BOOL:${TEST_PSA_API}>:${CMAKE_CURRENT_SOURCE_DIR}/pal_plat_test.c> +) + +target_include_directories(platform_ns + PUBLIC + . + common + ${HAL_NORDIC_PATH}/nrfx + ${HAL_NORDIC_PATH}/nrfx/mdk + ${HAL_NORDIC_PATH}/nrfx/drivers/include + ${PLATFORM_DIR}/include + ${PLATFORM_DIR}/ext/cmsis + ${PLATFORM_DIR}/ext/driver + ${PLATFORM_DIR}/ext/common + services/include +) + +target_compile_definitions(platform_ns + PUBLIC + $<$<BOOL:${TEST_PSA_API}>:PSA_API_TEST_ENABLED> + NRF_TRUSTZONE_NONSECURE + DOMAIN_NS=1 +) + +target_compile_definitions(platform_ns + PUBLIC + # We don't need to trim the device in the non-secure image because it + # is the secure image's responsiblity to do this. + NRF_DISABLE_FICR_TRIMCNF + # The glitch detector can only be configured from a secure image so + # we need to skip this configuration. + NRF_SKIP_GLITCHDETECTOR_DISABLE +) + diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/cmsis_drivers/Driver_Flash.c b/nrfdemo/build/tfm/api_ns/platform/common/core/cmsis_drivers/Driver_Flash.c new file mode 100644 index 0000000..e143634 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/cmsis_drivers/Driver_Flash.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include <Driver_Flash.h> +#include <RTE_Device.h> +#include <flash_layout.h> +#include <string.h> + +#include <nrf.h> + +#include <autoconf.h> + +#if defined(NRF_NVMC_S) +#include <nrfx_nvmc.h> +#elif defined(NRF_RRAMC_S) +#include <nrfx_rramc.h> + +#if CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE > 0 +#define WRITE_BUFFER_SIZE CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE +#else +#define WRITE_BUFFER_SIZE 0 +#endif + +#else +#error "Unrecognized platform" +#endif + +#ifndef ARG_UNUSED +#define ARG_UNUSED(arg) (void)arg +#endif + +#if RTE_FLASH0 + +/** + * Data width values for ARM_FLASH_CAPABILITIES::data_width + * \ref ARM_FLASH_CAPABILITIES + */ +enum { + DATA_WIDTH_8BIT = 0u, + DATA_WIDTH_16BIT, + DATA_WIDTH_32BIT, + DATA_WIDTH_ENUM_SIZE +}; + +static const uint32_t data_width_byte[DATA_WIDTH_ENUM_SIZE] = { + sizeof(uint8_t), + sizeof(uint16_t), + sizeof(uint32_t), +}; + +static const ARM_FLASH_CAPABILITIES DriverCapabilities = { + .event_ready = 0, + .data_width = DATA_WIDTH_32BIT, + .erase_chip = 0 +}; + +static ARM_FLASH_INFO FlashInfo = { + .sector_info = NULL, /* Uniform sector layout */ + .sector_count = FLASH_TOTAL_SIZE / FLASH_AREA_IMAGE_SECTOR_SIZE, + .sector_size = FLASH_AREA_IMAGE_SECTOR_SIZE, + /* page_size denotes the optimal programming page size in bytes + * for fast programming, but is currently unused by TF-M. */ + .page_size = sizeof(uint32_t), + /* Note that program_unit must match TFM_HAL_ITS_PROGRAM_UNIT */ + .program_unit = sizeof(uint32_t), + .erased_value = 0xFF +}; + +static bool is_range_valid(uint32_t addr, uint32_t cnt) +{ + uint32_t start_offset = (addr - FLASH_BASE_ADDRESS); + + if (start_offset > FLASH_TOTAL_SIZE) { + return false; + } + + if (cnt > (FLASH_TOTAL_SIZE - start_offset)) { + return false; + } + + return true; +} + +static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void) +{ + return DriverCapabilities; +} + +static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event) +{ + ARG_UNUSED(cb_event); + + if (DriverCapabilities.data_width >= DATA_WIDTH_ENUM_SIZE) { + return ARM_DRIVER_ERROR; + } + +#ifdef RRAMC_PRESENT + nrfx_rramc_config_t config = NRFX_RRAMC_DEFAULT_CONFIG(WRITE_BUFFER_SIZE); + + config.mode_write = true; + +#if CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE > 0 + config.preload_timeout_enable = true; + config.preload_timeout = CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE; +#else + config.preload_timeout_enable = false; + config.preload_timeout = 0; +#endif + + /* Don't use an event handler until it's understood whether we + * want it or not + */ + nrfx_rramc_evt_handler_t handler = NULL; + + nrfx_err_t err = nrfx_rramc_init(&config, handler); + + if(err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { + return err; + } +#endif /* RRAMC_PRESENT */ + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt) +{ + /* Conversion between data items and bytes */ + uint32_t bytes = cnt * data_width_byte[DriverCapabilities.data_width]; + + if (!is_range_valid(addr, bytes)) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + memcpy(data, (const void *)addr, bytes); + + return cnt; +} + +static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, + uint32_t cnt) +{ + /* Conversion between data items and bytes */ + uint32_t bytes = cnt * data_width_byte[DriverCapabilities.data_width]; + + /* Only aligned writes of full 32-bit words are allowed. */ + if (addr % sizeof(uint32_t)) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + if (!is_range_valid(addr, bytes)) { + return ARM_DRIVER_ERROR_PARAMETER; + } + +#ifdef NRF_NVMC_S + nrfx_nvmc_words_write(addr, data, cnt); +#else + nrfx_rramc_words_write(addr, data, cnt); + + /* At time of writing, the Zephyr driver commits writes, but the + * nrfx driver does not, so we commit here using the HAL to align + * Zephyr and TF-M behaviour. + * + * Not committing may cause data loss and/or high power + * consumption. + */ + nrf_rramc_task_trigger(NRF_RRAMC, NRF_RRAMC_TASK_COMMIT_WRITEBUF); +#endif + + /* Conversion between bytes and data items */ + return cnt; +} + +static int32_t ARM_Flash_EraseSector(uint32_t addr) +{ +#ifdef NRF_NVMC_S + nrfx_err_t err_code = nrfx_nvmc_page_erase(addr); + + if (err_code != NRFX_SUCCESS) { + return ARM_DRIVER_ERROR_PARAMETER; + } +#else + for (uint32_t *erase_word_ptr = (uint32_t *)addr; + (uint32_t)erase_word_ptr < addr + FLASH_AREA_IMAGE_SECTOR_SIZE; erase_word_ptr++) { + if(*erase_word_ptr != 0xFFFFFFFFU) { + nrfx_rramc_word_write((uint32_t)erase_word_ptr, 0xFFFFFFFFU); + } + } + + nrf_rramc_task_trigger(NRF_RRAMC, NRF_RRAMC_TASK_COMMIT_WRITEBUF); +#endif + + return ARM_DRIVER_OK; +} + +static ARM_FLASH_INFO * ARM_Flash_GetInfo(void) +{ + return &FlashInfo; +} + +ARM_DRIVER_FLASH Driver_FLASH0 = { + .GetVersion = NULL, + .GetCapabilities = ARM_Flash_GetCapabilities, + .Initialize = ARM_Flash_Initialize, + .Uninitialize = NULL, + .PowerControl = NULL, + .ReadData = ARM_Flash_ReadData, + .ProgramData = ARM_Flash_ProgramData, + .EraseSector = ARM_Flash_EraseSector, + .EraseChip = NULL, + .GetStatus = NULL, + .GetInfo = ARM_Flash_GetInfo +}; + +#endif /* RTE_FLASH0 */ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/cmsis_drivers/Driver_USART.c b/nrfdemo/build/tfm/api_ns/platform/common/core/cmsis_drivers/Driver_USART.c new file mode 100644 index 0000000..42053eb --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/cmsis_drivers/Driver_USART.c @@ -0,0 +1,463 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * Copyright (c) 2020-2021 Nordic Semiconductor ASA. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include <Driver_USART.h> +#include <RTE_Device.h> +#include <nrfx_uarte.h> +#include <string.h> +#include <stdint.h> +#include <nrf-pinctrl.h> + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0])) +#endif + +// TODO: NCSDK-22597: Support configuring peripherals as secure +#if !(DOMAIN_NS == 1U) && defined(CONFIG_TFM_LOG_SHARE_UART) && defined(NRF_SPU) +#define SPU_CONFIGURE_UART +#include <spu.h> +#endif + +#ifndef ARG_UNUSED +#define ARG_UNUSED(arg) (void)arg +#endif + +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2) + +#if RTE_USART0 || RTE_USART1 || RTE_USART2 || RTE_USART3 || \ + RTE_UART00 || RTE_USART20 || RTE_UART21 || RTE_UART22 || RTE_USART30 + +#define PSEL_DISCONNECTED 0xFFFFFFFFUL + +#define UART_CONFIG_INITIALIZER() \ +{ \ + .txd_pin = PSEL_DISCONNECTED, \ + .rxd_pin = PSEL_DISCONNECTED, \ + .rts_pin = PSEL_DISCONNECTED, \ + .cts_pin = PSEL_DISCONNECTED, \ + .baudrate = NRF_UARTE_BAUDRATE_115200, \ + .interrupt_priority = NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY, \ + .config = { \ + .hwfc = NRF_UARTE_HWFC_DISABLED, \ + .parity = NRF_UARTE_PARITY_EXCLUDED, \ + .stop = NRF_UARTE_STOP_ONE, \ + }, \ +} + +void uart_config_set_uart_pins(nrfx_uarte_config_t *uart_config, + const uint32_t uart_pins[], + size_t uart_pins_count) +{ + for (size_t i = 0; i < uart_pins_count; i++) { + uint32_t psel = NRF_GET_PIN(uart_pins[i]); + + if (psel == NRF_PIN_DISCONNECTED) { + psel = PSEL_DISCONNECTED; + } + + switch (NRF_GET_FUN(uart_pins[i])) { + case NRF_FUN_UART_TX: uart_config->txd_pin = psel; break; + case NRF_FUN_UART_RX: uart_config->rxd_pin = psel; break; + case NRF_FUN_UART_RTS: uart_config->rts_pin = psel; break; + case NRF_FUN_UART_CTS: uart_config->cts_pin = psel; break; + } + } +} + +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_USART_API_VERSION, + ARM_USART_DRV_VERSION +}; + +static const ARM_USART_CAPABILITIES DriverCapabilities = { + .asynchronous = 1, +}; + +typedef struct { + const nrfx_uarte_t uarte; + const uint32_t *uart_pins; + size_t uart_pins_count; + size_t tx_count; + size_t rx_count; + nrf_uarte_config_t hal_cfg; + nrf_uarte_baudrate_t baudrate; + bool initialized; +} UARTx_Resources; + +static ARM_DRIVER_VERSION ARM_USART_GetVersion(void) +{ + return DriverVersion; +} + +static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void) +{ + return DriverCapabilities; +} + +static int32_t ARM_USARTx_Initialize(ARM_USART_SignalEvent_t cb_event, + UARTx_Resources *uart_resources) +{ + ARG_UNUSED(cb_event); + +#ifdef SPU_CONFIGURE_UART + spu_peripheral_config_secure((uint32_t)uart_resources->uarte.p_reg, false); + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET((uint32_t)uart_resources->uarte.p_reg)); +#endif + + nrfx_uarte_config_t uart_config = UART_CONFIG_INITIALIZER(); + + uart_config_set_uart_pins(&uart_config, + uart_resources->uart_pins, + uart_resources->uart_pins_count); + + nrfx_err_t err_code = nrfx_uarte_init(&uart_resources->uarte, + &uart_config, + NULL); + if (err_code != NRFX_SUCCESS) { + return ARM_DRIVER_ERROR_BUSY; + } + + uart_resources->tx_count = 0; + uart_resources->rx_count = 0; + uart_resources->hal_cfg = uart_config.config; + uart_resources->baudrate = uart_config.baudrate; + + uart_resources->initialized = true; + return ARM_DRIVER_OK; +} + +static int32_t ARM_USARTx_Uninitialize(UARTx_Resources *uart_resources) +{ + nrfx_uarte_uninit(&uart_resources->uarte); + + uart_resources->initialized = false; + +#ifdef SPU_CONFIGURE_UART + spu_peripheral_config_non_secure((uint32_t)uart_resources->uarte.p_reg, false); + NVIC_SetTargetState(NRFX_IRQ_NUMBER_GET((uint32_t)uart_resources->uarte.p_reg)); +#endif + + return ARM_DRIVER_OK; +} + +static int32_t ARM_USARTx_PowerControl(ARM_POWER_STATE state, + UARTx_Resources *uart_resources) +{ + ARG_UNUSED(uart_resources); + + switch (state) { + case ARM_POWER_FULL: + /* Nothing to be done */ + return ARM_DRIVER_OK; + + case ARM_POWER_OFF: + case ARM_POWER_LOW: + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } +} + +#ifndef MIN +#define MIN(a,b) (((a) <= (b)) ? (a) : (b)); +#endif + +#define SEND_RAM_BUF_SIZE 64 + +static int32_t ARM_USARTx_Send(const void *data, uint32_t num, + UARTx_Resources *uart_resources) +{ + if (!uart_resources->initialized) { + return ARM_DRIVER_ERROR; + } + + /* nrfx_uarte_tx() only supports input data from RAM. */ + if (!nrfx_is_in_ram(data)) { + uint8_t ram_buf[SEND_RAM_BUF_SIZE]; + + for (uint32_t offs = 0; offs < num; offs += sizeof(ram_buf)) { + uint32_t len = MIN(num - offs, sizeof(ram_buf)); + memcpy(ram_buf, data + offs, len); + int32_t cmsis_err = ARM_USARTx_Send(ram_buf, len, uart_resources); + if (cmsis_err != ARM_DRIVER_OK) { + return cmsis_err; + } + } + } else { + nrfx_err_t err_code = nrfx_uarte_tx(&uart_resources->uarte, data, num, 0); + if (err_code == NRFX_ERROR_BUSY) { + return ARM_DRIVER_ERROR_BUSY; + } else if (err_code != NRFX_SUCCESS) { + return ARM_DRIVER_ERROR; + } + + uart_resources->tx_count = num; + } + + return ARM_DRIVER_OK; +} + +static int32_t ARM_USARTx_Receive(void *data, uint32_t num, + UARTx_Resources *uart_resources) +{ + if (!uart_resources->initialized) { + return ARM_DRIVER_ERROR; + } + + nrfx_err_t err_code = nrfx_uarte_rx(&uart_resources->uarte, data, num); + if (err_code == NRFX_ERROR_BUSY) { + return ARM_DRIVER_ERROR_BUSY; + } else if (err_code != NRFX_SUCCESS) { + return ARM_DRIVER_ERROR; + } + + uart_resources->rx_count = num; + return ARM_DRIVER_OK; +} + +static int32_t ARM_USART_Transfer(const void *data_out, void *data_in, + uint32_t num) +{ + ARG_UNUSED(data_out); + ARG_UNUSED(data_in); + ARG_UNUSED(num); + + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static uint32_t ARM_USARTx_GetTxCount(const UARTx_Resources *uart_resources) +{ + return uart_resources->tx_count; +} + +static uint32_t ARM_USARTx_GetRxCount(const UARTx_Resources *uart_resources) +{ + return uart_resources->rx_count; +} + +static int32_t ARM_USARTx_Control(uint32_t control, uint32_t arg, + UARTx_Resources *uart_resources) +{ + if ((control & ARM_USART_CONTROL_Msk) != ARM_USART_MODE_ASYNCHRONOUS) { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + nrf_uarte_baudrate_t baudrate = uart_resources->baudrate; + nrf_uarte_config_t hal_cfg = uart_resources->hal_cfg; + switch (arg) { + case 1200: baudrate = NRF_UARTE_BAUDRATE_1200; break; + case 2400: baudrate = NRF_UARTE_BAUDRATE_2400; break; + case 4800: baudrate = NRF_UARTE_BAUDRATE_4800; break; + case 9600: baudrate = NRF_UARTE_BAUDRATE_9600; break; + case 14400: baudrate = NRF_UARTE_BAUDRATE_14400; break; + case 19200: baudrate = NRF_UARTE_BAUDRATE_19200; break; + case 28800: baudrate = NRF_UARTE_BAUDRATE_28800; break; + case 31250: baudrate = NRF_UARTE_BAUDRATE_31250; break; + case 38400: baudrate = NRF_UARTE_BAUDRATE_38400; break; + case 56000: baudrate = NRF_UARTE_BAUDRATE_56000; break; + case 57600: baudrate = NRF_UARTE_BAUDRATE_57600; break; + case 76800: baudrate = NRF_UARTE_BAUDRATE_76800; break; + case 115200: baudrate = NRF_UARTE_BAUDRATE_115200; break; + case 230400: baudrate = NRF_UARTE_BAUDRATE_230400; break; + case 250000: baudrate = NRF_UARTE_BAUDRATE_250000; break; + case 460800: baudrate = NRF_UARTE_BAUDRATE_460800; break; + case 921600: baudrate = NRF_UARTE_BAUDRATE_921600; break; + case 1000000: baudrate = NRF_UARTE_BAUDRATE_1000000; break; + default: + return ARM_USART_ERROR_BAUDRATE; + } + + if ((control & ARM_USART_DATA_BITS_Msk) != ARM_USART_DATA_BITS_8) { + return ARM_USART_ERROR_DATA_BITS; + } + + switch (control & ARM_USART_STOP_BITS_Msk) { + case ARM_USART_STOP_BITS_1: + hal_cfg.stop = NRF_UARTE_STOP_ONE; + break; + + case ARM_USART_STOP_BITS_2: + hal_cfg.stop = NRF_UARTE_STOP_TWO; + break; + + default: + return ARM_USART_ERROR_STOP_BITS; + } + + switch (control & ARM_USART_PARITY_Msk) { + case ARM_USART_PARITY_NONE: + hal_cfg.parity = NRF_UARTE_PARITY_EXCLUDED; + break; + +#if defined(UARTE_CONFIG_PARITYTYPE_Msk) + case ARM_USART_PARITY_EVEN: + hal_cfg.parity = NRF_UARTE_PARITY_INCLUDED; + hal_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN; + break; + + case ARM_USART_PARITY_ODD: + hal_cfg.parity = NRF_UARTE_PARITY_INCLUDED; + hal_cfg.paritytype = NRF_UARTE_PARITYTYPE_ODD; + break; +#else + case ARM_USART_PARITY_EVEN: + hal_cfg.parity = NRF_UARTE_PARITY_INCLUDED; + break; +#endif + + default: + return ARM_USART_ERROR_PARITY; + } + + switch (control & ARM_USART_FLOW_CONTROL_Msk) { + case ARM_USART_FLOW_CONTROL_NONE: + hal_cfg.hwfc = NRF_UARTE_HWFC_DISABLED; + break; + + case ARM_USART_FLOW_CONTROL_RTS_CTS: + hal_cfg.hwfc = NRF_UARTE_HWFC_ENABLED; + break; + + default: + return ARM_USART_ERROR_FLOW_CONTROL; + } + + uart_resources->baudrate = baudrate; + uart_resources->hal_cfg = hal_cfg; + + nrf_uarte_baudrate_set(uart_resources->uarte.p_reg, + uart_resources->baudrate); + nrf_uarte_configure(uart_resources->uarte.p_reg, + &uart_resources->hal_cfg); + + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS ARM_USART_GetStatus(void) +{ + ARM_USART_STATUS status = {0}; + return status; +} + +static int32_t ARM_USART_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + ARG_UNUSED(control); + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS status = {0}; + return status; +} + +#define DRIVER_USART(idx) \ + static const uint32_t UART##idx##_pins[] = RTE_USART##idx##_PINS; \ + static UARTx_Resources UART##idx##_Resources = { \ + .uarte = NRFX_UARTE_INSTANCE(idx), \ + .uart_pins = UART##idx##_pins, \ + .uart_pins_count = ARRAY_SIZE(UART##idx##_pins) \ + }; \ + static int32_t ARM_USART##idx##_Initialize( \ + ARM_USART_SignalEvent_t cb_event) \ + { \ + return ARM_USARTx_Initialize(cb_event, &UART##idx##_Resources); \ + } \ + static int32_t ARM_USART##idx##_Uninitialize(void) \ + { \ + return ARM_USARTx_Uninitialize(&UART##idx##_Resources); \ + } \ + static int32_t ARM_USART##idx##_PowerControl(ARM_POWER_STATE state) \ + { \ + return ARM_USARTx_PowerControl(state, &UART##idx##_Resources); \ + } \ + static int32_t ARM_USART##idx##_Send(const void *data, uint32_t num) \ + { \ + return ARM_USARTx_Send(data, num, &UART##idx##_Resources); \ + } \ + static int32_t ARM_USART##idx##_Receive(void *data, uint32_t num) \ + { \ + return ARM_USARTx_Receive(data, num, &UART##idx##_Resources); \ + } \ + static uint32_t ARM_USART##idx##_GetTxCount(void) \ + { \ + return ARM_USARTx_GetTxCount(&UART##idx##_Resources); \ + } \ + static uint32_t ARM_USART##idx##_GetRxCount(void) \ + { \ + return ARM_USARTx_GetRxCount(&UART##idx##_Resources); \ + } \ + static int32_t ARM_USART##idx##_Control(uint32_t control, \ + uint32_t arg) \ + { \ + return ARM_USARTx_Control(control, arg, &UART##idx##_Resources); \ + } \ + ARM_DRIVER_USART Driver_USART##idx = { \ + .GetVersion = ARM_USART_GetVersion, \ + .GetCapabilities = ARM_USART_GetCapabilities, \ + .Initialize = ARM_USART##idx##_Initialize, \ + .Uninitialize = ARM_USART##idx##_Uninitialize, \ + .PowerControl = ARM_USART##idx##_PowerControl, \ + .Send = ARM_USART##idx##_Send, \ + .Receive = ARM_USART##idx##_Receive, \ + .Transfer = ARM_USART_Transfer, \ + .GetTxCount = ARM_USART##idx##_GetTxCount, \ + .GetRxCount = ARM_USART##idx##_GetRxCount, \ + .Control = ARM_USART##idx##_Control, \ + .GetStatus = ARM_USART_GetStatus, \ + .SetModemControl = ARM_USART_SetModemControl, \ + .GetModemStatus = ARM_USART_GetModemStatus \ + } + +#if RTE_USART0 +DRIVER_USART(0); +#endif + +#if RTE_USART1 +DRIVER_USART(1); +#endif + +#if RTE_USART2 +DRIVER_USART(2); +#endif + +#if RTE_USART3 +DRIVER_USART(3); +#endif + +#if RTE_USART00 +DRIVER_USART(00); +#endif + +#if RTE_USART20 +DRIVER_USART(20); +#endif + +#if RTE_USART21 +DRIVER_USART(21); +#endif + +#if RTE_USART22 +DRIVER_USART(22); +#endif + +#if RTE_USART30 +DRIVER_USART(30); +#endif + +#endif /* RTE_USART0 || RTE_USART1 || etc. */ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/common/cmsis.h b/nrfdemo/build/tfm/api_ns/platform/common/core/common/cmsis.h new file mode 100644 index 0000000..f2ffa43 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/common/cmsis.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NORDIC_NRF_CMSIS_H__ +#define __NORDIC_NRF_CMSIS_H__ + +#include <nrf.h> + +#endif /*__NORDIC_NRF_CMSIS_H__*/ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/common/nrf-pinctrl.h b/nrfdemo/build/tfm/api_ns/platform/common/core/common/nrf-pinctrl.h new file mode 100644 index 0000000..5d2b1da --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/common/nrf-pinctrl.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NRF_INCLUDE_NRF_PINCTRL_H +#define NRF_INCLUDE_NRF_PINCTRL_H + +/* + * The whole nRF pin configuration information is encoded in a 32-bit bitfield + * organized as follows: + * + * - 31..16: Pin function. + * - 15: Reserved. + * - 14: Pin inversion mode. + * - 13: Pin low power mode. + * - 12..9: Pin output drive configuration. + * - 8..7: Pin pull configuration. + * - 6..0: Pin number (combination of port and pin). + */ + +/** + * @name nRF pin configuration bit field positions and masks. + * @{ + */ + +/** Position of the function field. */ +#define NRF_FUN_POS 16U +/** Mask for the function field. */ +#define NRF_FUN_MSK 0xFFFFU +/** Position of the invert field. */ +#define NRF_INVERT_POS 14U +/** Mask for the invert field. */ +#define NRF_INVERT_MSK 0x1U +/** Position of the low power field. */ +#define NRF_LP_POS 13U +/** Mask for the low power field. */ +#define NRF_LP_MSK 0x1U +/** Position of the drive configuration field. */ +#define NRF_DRIVE_POS 9U +/** Mask for the drive configuration field. */ +#define NRF_DRIVE_MSK 0xFU +/** Position of the pull configuration field. */ +#define NRF_PULL_POS 7U +/** Mask for the pull configuration field. */ +#define NRF_PULL_MSK 0x3U +/** Position of the pin field. */ +#define NRF_PIN_POS 0U +/** Mask for the pin field. */ +#define NRF_PIN_MSK 0x7FU + +/** @} */ + +/** + * @name nRF pinctrl pin functions. + * @{ + */ + +/** UART TX */ +#define NRF_FUN_UART_TX 0U +/** UART RX */ +#define NRF_FUN_UART_RX 1U +/** UART RTS */ +#define NRF_FUN_UART_RTS 2U +/** UART CTS */ +#define NRF_FUN_UART_CTS 3U + +/** Indicates that a pin is disconnected */ +#define NRF_PIN_DISCONNECTED NRF_PIN_MSK + +/** @} */ + +/** + * @brief Utility macro to build nRF psels property entry. + * + * @param fun Pin function configuration (see NRF_FUNC_{name} macros). + * @param port Port (0 or 1). + * @param pin Pin (0..31). + */ +#define NRF_PSEL(fun, port, pin) \ + ((((((port) * 32U) + (pin)) & NRF_PIN_MSK) << NRF_PIN_POS) | \ + ((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS)) + +/** + * @brief Utility macro to build nRF psels property entry when a pin is disconnected. + * + * This can be useful in situations where code running before Zephyr, e.g. a bootloader + * configures pins that later needs to be disconnected. + * + * @param fun Pin function configuration (see NRF_FUN_{name} macros). + */ +#define NRF_PSEL_DISCONNECTED(fun) \ + (NRF_PIN_DISCONNECTED | \ + ((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS)) + +/** + * @brief Utility macro to obtain pin function. + * + * @param pincfg Pin configuration bit field. + */ +#define NRF_GET_FUN(pincfg) (((pincfg) >> NRF_FUN_POS) & NRF_FUN_MSK) + + +/** + * @brief Utility macro to obtain port and pin combination. + * + * @param pincfg Pin configuration bit field. + */ +#define NRF_GET_PIN(pincfg) (((pincfg) >> NRF_PIN_POS) & NRF_PIN_MSK) + +#endif /* NRF_INCLUDE_NRF_PINCTRL_H */ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/common/nrfx_glue.h b/nrfdemo/build/tfm/api_ns/platform/common/core/common/nrfx_glue.h new file mode 100644 index 0000000..fcff207 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/common/nrfx_glue.h @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_GLUE_H__ +#define NRFX_GLUE_H__ + +#include <assert.h> + +#include <soc/nrfx_coredep.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_glue nrfx_glue.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for placing a runtime assertion. + * + * @param expression Expression to be evaluated. + */ +#if defined(NDEBUG) +#define NRFX_ASSERT(expression) if (0 && (expression)) {} +#else +#define NRFX_ASSERT(expression) assert(expression) +#endif + +/** + * @brief Macro for placing a compile time assertion. + * + * @param expression Expression to be evaluated. + */ +#define NRFX_STATIC_ASSERT(expression) _Static_assert(expression, "") + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for setting the priority of a specific IRQ. + * + * @param irq_number IRQ number. + * @param priority Priority to be set. + */ +#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) \ + NVIC_SetPriority(irq_number, priority) + +/** + * @brief Macro for enabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_ENABLE(irq_number) NVIC_EnableIRQ(irq_number) + +/** + * @brief Macro for checking if a specific IRQ is enabled. + * + * @param irq_number IRQ number. + * + * @retval true If the IRQ is enabled. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_ENABLED(irq_number) NVIC_GetEnableIRQ(irq_number) + +/** + * @brief Macro for disabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_DISABLE(irq_number) NVIC_DisableIRQ(irq_number) + +/** + * @brief Macro for setting a specific IRQ as pending. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_SET(irq_number) NVIC_SetPendingIRQ(irq_number) + +/** + * @brief Macro for clearing the pending status of a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_CLEAR(irq_number) NVIC_ClearPendingIRQ(irq_number) + +/** + * @brief Macro for checking the pending status of a specific IRQ. + * + * @retval true If the IRQ is pending. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_PENDING(irq_number) NVIC_GetPendingIRQ(irq_number) + +/** @brief Macro for entering into a critical section. */ +#define NRFX_CRITICAL_SECTION_ENTER() nrfx_critical_section_enter() +void nrfx_critical_section_enter(void); + +/** @brief Macro for exiting from a critical section. */ +#define NRFX_CRITICAL_SECTION_EXIT() nrfx_critical_section_exit() +void nrfx_critical_section_exit(void); + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that + * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. + * A compilation error is generated if the DWT unit is not present + * in the SoC used. + */ +#define NRFX_DELAY_DWT_BASED 0 + +/** + * @brief Macro for delaying the code execution for at least the specified time. + * + * @param us_time Number of microseconds to wait. + */ +#define NRFX_DELAY_US(us_time) nrfx_coredep_delay_us(us_time) + +//------------------------------------------------------------------------------ + +/** @brief Atomic 32-bit unsigned type. */ +#define nrfx_atomic_t long + +/** + * @brief Macro for storing a value to an atomic object and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value to store. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_STORE(p_data, value) __atomic_exchange_n(p_data, value, __ATOMIC_SEQ_CST) + +/** + * @brief Macro for running a bitwise OR operation on an atomic object and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the OR operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_OR(p_data, value) __atomic_fetch_or(p_data, value, __ATOMIC_SEQ_CST) + +/** + * @brief Macro for running a bitwise AND operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the AND operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_AND(p_data, value) __atomic_fetch_and(p_data, value, __ATOMIC_SEQ_CST) + +/** + * @brief Macro for running a bitwise XOR operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the XOR operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_XOR(p_data, value) __atomic_fetch_xor(p_data, value, __ATOMIC_SEQ_CST) + +/** + * @brief Macro for running an addition operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the ADD operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_ADD(p_data, value) __atomic_fetch_add(p_data, value, __ATOMIC_SEQ_CST) + +/** + * @brief Macro for running a subtraction operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the SUB operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_SUB(p_data, value) __atomic_fetch_sub(p_data, value, __ATOMIC_SEQ_CST) + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that the + * @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined + * in a customized way and the default definitions from @c <nrfx_error.h> + * should not be used. + */ +#define NRFX_CUSTOM_ERROR_CODES 0 + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that inside HALs + * the event registers are read back after clearing, on devices that + * otherwise could defer the actual register modification. + */ +#define NRFX_EVENT_READBACK_ENABLED 1 + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for writing back cache lines associated with the specified buffer. + * + * @param[in] p_buffer Pointer to the buffer. + * @param[in] size Size of the buffer. + */ +#define NRFY_CACHE_WB(p_buffer, size) \ + do { \ + (void)p_buffer; \ + (void)size; \ + } while (0) + +/** + * @brief Macro for invalidating cache lines associated with the specified buffer. + * + * @param[in] p_buffer Pointer to the buffer. + * @param[in] size Size of the buffer. + */ +#define NRFY_CACHE_INV(p_buffer, size) \ + do { \ + (void)p_buffer; \ + (void)size; \ + } while (0) + +/** + * @brief Macro for writing back and invalidating cache lines associated with + * the specified buffer. + * + * @param[in] p_buffer Pointer to the buffer. + * @param[in] size Size of the buffer. + */ +#define NRFY_CACHE_WBINV(p_buffer, size) \ + do { \ + (void)p_buffer; \ + (void)size; \ + } while (0) + +//------------------------------------------------------------------------------ + +/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI_CHANNELS_USED 0 + +/** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI_GROUPS_USED 0 + +/** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */ +#define NRFX_PPI_CHANNELS_USED 0 + +/** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */ +#define NRFX_PPI_GROUPS_USED 0 + +/** @brief Bitmask that defines GPIOTE channels that are reserved for use outside of the nrfx library. */ +#define NRFX_GPIOTE_CHANNELS_USED 0 + +/** @brief Bitmask that defines EGU instances that are reserved for use outside of the nrfx library. */ +#define NRFX_EGUS_USED 0 + +/** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */ +#define NRFX_TIMERS_USED 0 + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_GLUE_H__ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/common/nrfx_log.h b/nrfdemo/build/tfm/api_ns/platform/common/core/common/nrfx_log.h new file mode 100644 index 0000000..80d8efb --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/common/nrfx_log.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_LOG_H__ +#define NRFX_LOG_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_log nrfx_log.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +/** + * @brief Macro for logging a message with the severity level ERROR. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_ERROR(format, ...) + +/** + * @brief Macro for logging a message with the severity level WARNING. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_WARNING(format, ...) + +/** + * @brief Macro for logging a message with the severity level INFO. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_INFO(format, ...) + +/** + * @brief Macro for logging a message with the severity level DEBUG. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_DEBUG(format, ...) + + +/** + * @brief Macro for logging a memory dump with the severity level ERROR. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level WARNING. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level INFO. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_INFO(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level DEBUG. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length) + + +/** + * @brief Macro for getting the textual representation of a given error code. + * + * @param[in] error_code Error code. + * + * @return String containing the textual representation of the error code. + */ +#define NRFX_LOG_ERROR_STRING_GET(error_code) + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_LOG_H__ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/common/tfm_hal_platform_common.h b/nrfdemo/build/tfm/api_ns/platform/common/core/common/tfm_hal_platform_common.h new file mode 100644 index 0000000..787c2e1 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/common/tfm_hal_platform_common.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __TFM_HAL_PLATFORM_COMMON_H__ +#define __TFM_HAL_PLATFORM_COMMON_H__ + +#include "tfm_plat_defs.h" + +enum tfm_hal_status_t tfm_hal_platform_common_init(void); + +#endif /* __TFM_HAL_PLATFORM_COMMON_H__ */ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/config.cmake b/nrfdemo/build/tfm/api_ns/platform/common/core/config.cmake new file mode 100644 index 0000000..07e8682 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/config.cmake @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2022-2023, Arm Limited. All rights reserved. +# Copyright (c) 2021, Nordic Semiconductor ASA. +# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) +# or an affiliate of Cypress Semiconductor Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +set(HAL_NORDIC_PATH "DOWNLOAD" CACHE PATH "Path to the Nordic HAL (or DOWNLOAD to fetch automatically)") +set(HAL_NORDIC_VERSION "nrfx-3.0.0" CACHE STRING "Version of the Nordic HAL to download") +set(HAL_NORDIC_REMOTE "https://github.com/zephyrproject-rtos/hal_nordic" CACHE STRING "Remote of the Nordic HAL to download") +# Set to FALSE if HAL_NORDIC_VERSION is a SHA. +set(HAL_NORDIC_SHALLOW_FETCH CACHE BOOL TRUE "Use shallow fetch to download Nordic HAL.") + +set(NULL_POINTER_EXCEPTION_DETECTION FALSE CACHE BOOL + "Enable null-pointer dereference detection for \ + priviliged and unpriviliged secure reads and writes on supported platforms. \ + Can be used to debug faults in the SPE. \ + Note that null-pointer dereferences from the NSPE \ + will trigger SecureFaults even without this option enabled. \ + May require more MPU regions than are available depending on the configuration." + ) + +# Required if MCUBoot has been built without CONFIG_MCUBOOT_CLEANUP_ARM_CORE enabled +set(NRF_HW_INIT_RESET_ON_BOOT OFF CACHE BOOL "Initialize internal architecture state at boot") + +# Required if MCUboot has been built without CONFIG_MCUBOOT_NRF_CLEANUP_PERIPHERAL enabled. +set(NRF_HW_INIT_NRF_PERIPHERALS OFF CACHE BOOL "Initialize nRF peripherals at boot") + +if (NRF_HW_INIT_NRF_PERIPHERALS AND NOT NRF_HW_INIT_RESET_ON_BOOT) + message(FATAL_ERROR "NRF_HW_INIT_NRF_PERIPHERALS depends on NRF_HW_INIT_RESET_ON_BOOT") +endif() + +# Platform-specific configurations +set(CONFIG_TFM_USE_TRUSTZONE ON) +set(TFM_MULTI_CORE_TOPOLOGY OFF) + +set(NRF_SECURE_UART_INSTANCE 1 CACHE STRING "The UART instance number to use for secure UART") diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/config_nordic_nrf_spe.cmake b/nrfdemo/build/tfm/api_ns/platform/common/core/config_nordic_nrf_spe.cmake new file mode 100644 index 0000000..6c353db --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/config_nordic_nrf_spe.cmake @@ -0,0 +1,7 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(HAL_NORDIC_PATH /home/mike/Documents/ncs/v2.7.0/modules/hal/nordic CACHE STRING "Path to nordic HAL" FORCE) diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/native_drivers/mpu_armv8m_drv.c b/nrfdemo/build/tfm/api_ns/platform/common/core/native_drivers/mpu_armv8m_drv.c new file mode 100644 index 0000000..5a64e18 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/native_drivers/mpu_armv8m_drv.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2017-2019, Arm Limited. All rights reserved. + * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon + * company) or an affiliate of Cypress Semiconductor Corporation. All rights + * reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "mpu_armv8m_drv.h" +#include "cmsis.h" + +/* + * FixMe: + * This is a beta quality driver for MPU in v8M. To be finalized. + */ + +enum mpu_armv8m_error_t mpu_armv8m_enable(struct mpu_armv8m_dev_t *dev, + uint32_t privdef_en, + uint32_t hfnmi_en) +{ + /*No error checking*/ + + MPU_Type *mpu = (MPU_Type *)dev->base; + + /* + * FixMe: Set 3 pre-defined MAIR_ATTR for memory. The attributes come + * from default memory map, need to check if fine-tune is necessary. + * + * MAIR0_0: Peripheral, Device-nGnRE. + * MAIR0_1: Code, WT RA. Same attr for Outer and Inner. + * MAIR0_2: SRAM, WBWA RA. Same attr for Outer and Inner. + */ + mpu->MAIR0 = (MPU_ARMV8M_MAIR_ATTR_DEVICE_VAL << MPU_MAIR0_Attr0_Pos) | + (MPU_ARMV8M_MAIR_ATTR_CODE_VAL << MPU_MAIR0_Attr1_Pos) | + (MPU_ARMV8M_MAIR_ATTR_DATA_VAL << MPU_MAIR0_Attr2_Pos); + + mpu->CTRL = + (privdef_en ? MPU_CTRL_PRIVDEFENA_Msk : 0) | + (hfnmi_en ? MPU_CTRL_HFNMIENA_Msk : 0); + + /*Ensure all configuration is written before enable*/ + + mpu->CTRL |= MPU_CTRL_ENABLE_Msk; + + /* Enable MPU before next instruction */ + __DSB(); + __ISB(); + return MPU_ARMV8M_OK; +} + +enum mpu_armv8m_error_t mpu_armv8m_disable(struct mpu_armv8m_dev_t *dev) +{ + MPU_Type *mpu = (MPU_Type *)dev->base; + + /* Reset all fields as enable does full setup */ + mpu->CTRL = 0; + + return MPU_ARMV8M_OK; +} + + +enum mpu_armv8m_error_t mpu_armv8m_region_enable( + struct mpu_armv8m_dev_t *dev, + struct mpu_armv8m_region_cfg_t *region_cfg) +{ + MPU_Type *mpu = (MPU_Type *)dev->base; + + enum mpu_armv8m_error_t ret_val = MPU_ARMV8M_OK; + uint32_t ctrl_before; + uint32_t base_cfg; + uint32_t limit_cfg; + + /*FIXME : Add complete error checking*/ + if ((region_cfg->region_base & ~MPU_RBAR_BASE_Msk) != 0) { + return MPU_ARMV8M_ERROR; + } + /* region_limit doesn't need to be aligned but the scatter + * file needs to be setup to ensure that partitions do not overlap. + */ + + uint32_t num_regions = + ((mpu->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos); + + if (region_cfg->region_nr >= num_regions) { + return MPU_ARMV8M_ERROR; + } + + ctrl_before = mpu->CTRL; + mpu->CTRL = 0; + + mpu->RNR = region_cfg->region_nr & MPU_RNR_REGION_Msk; + + /* This zeroes the lower bits of the base address */ + base_cfg = region_cfg->region_base & MPU_RBAR_BASE_Msk; + base_cfg |= (region_cfg->attr_sh << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk; + base_cfg |= (region_cfg->attr_access << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk; + base_cfg |= (region_cfg->attr_exec << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk; + + mpu->RBAR = base_cfg; + + /* This zeroes the lower bits of limit address but they are treated as 1 */ + limit_cfg = (region_cfg->region_limit-1) & MPU_RLAR_LIMIT_Msk; + + limit_cfg |= (region_cfg->region_attridx << MPU_RLAR_AttrIndx_Pos) & + MPU_RLAR_AttrIndx_Msk; + + limit_cfg |= MPU_RLAR_EN_Msk; + + mpu->RLAR = limit_cfg; + + /*Restore main MPU control*/ + mpu->CTRL = ctrl_before; + + /* Enable MPU before the next instruction */ + __DSB(); + __ISB(); + + return ret_val; +} + + +enum mpu_armv8m_error_t mpu_armv8m_region_disable( + struct mpu_armv8m_dev_t *dev, + uint32_t region_nr) +{ + + MPU_Type *mpu = (MPU_Type *)dev->base; + + enum mpu_armv8m_error_t ret_val = MPU_ARMV8M_OK; + uint32_t ctrl_before; + + /*FIXME : Add complete error checking*/ + + ctrl_before = mpu->CTRL; + mpu->CTRL = 0; + + mpu->RNR = region_nr & MPU_RNR_REGION_Msk; + + mpu->RBAR = 0; + mpu->RLAR = 0; + + /*Restore main MPU control*/ + mpu->CTRL = ctrl_before; + + return ret_val; +} + +enum mpu_armv8m_error_t mpu_armv8m_clean(struct mpu_armv8m_dev_t *dev) +{ + MPU_Type *mpu = (MPU_Type *)dev->base; + + uint32_t num_regions = + ((mpu->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos); + + for (uint32_t i = 0; i < num_regions; i++) { + mpu_armv8m_region_disable(dev, i); + } + + return MPU_ARMV8M_OK; + +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/native_drivers/mpu_armv8m_drv.h b/nrfdemo/build/tfm/api_ns/platform/common/core/native_drivers/mpu_armv8m_drv.h new file mode 100644 index 0000000..9244cdf --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/native_drivers/mpu_armv8m_drv.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2017-2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __MPU_ARMV8M_DRV_H__ +#define __MPU_ARMV8M_DRV_H__ + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define PRIVILEGED_DEFAULT_ENABLE 1 +#define HARDFAULT_NMI_ENABLE 1 + +/* MAIR_ATTR */ +#define MPU_ARMV8M_MAIR_ATTR_DEVICE_VAL 0x04 +#define MPU_ARMV8M_MAIR_ATTR_DEVICE_IDX 0 +#define MPU_ARMV8M_MAIR_ATTR_CODE_VAL 0xAA +#define MPU_ARMV8M_MAIR_ATTR_CODE_IDX 1 +#define MPU_ARMV8M_MAIR_ATTR_DATA_VAL 0xFF +#define MPU_ARMV8M_MAIR_ATTR_DATA_IDX 2 + +struct mpu_armv8m_dev_t { + const uint32_t base; +}; + +enum mpu_armv8m_error_t { + MPU_ARMV8M_OK, + MPU_ARMV8M_ERROR +}; + +enum mpu_armv8m_attr_exec_t { + MPU_ARMV8M_XN_EXEC_OK, + MPU_ARMV8M_XN_EXEC_NEVER +}; + +enum mpu_armv8m_attr_access_t { + MPU_ARMV8M_AP_RW_PRIV_ONLY, + MPU_ARMV8M_AP_RW_PRIV_UNPRIV, + MPU_ARMV8M_AP_RO_PRIV_ONLY, + MPU_ARMV8M_AP_RO_PRIV_UNPRIV +}; + +enum mpu_armv8m_attr_shared_t { + MPU_ARMV8M_SH_NONE, + MPU_ARMV8M_SH_UNUSED, + MPU_ARMV8M_SH_OUTER, + MPU_ARMV8M_SH_INNER +}; + +struct mpu_armv8m_region_cfg_t { + uint32_t region_nr; + uint32_t region_base; + uint32_t region_limit; + uint32_t region_attridx; + enum mpu_armv8m_attr_exec_t attr_exec; + enum mpu_armv8m_attr_access_t attr_access; + enum mpu_armv8m_attr_shared_t attr_sh; +}; + +struct mpu_armv8m_region_cfg_raw_t { + uint32_t region_nr; + uint32_t region_base; + uint32_t region_limit; +}; + + +/** + * \brief Enable MPU + * + * \param[in] dev MPU device \ref mpu_armv8m_dev_t + * \param[in] privdef_en privilege default region 1:enable 0:disable + * \param[in] hfnmi_en mpu for hard fault & nmi 1:enable 0:disable + * + * \return Error code \ref mpu_armv8m_error_t + * + * \note This function doesn't check if dev is NULL. + */ + +enum mpu_armv8m_error_t mpu_armv8m_enable(struct mpu_armv8m_dev_t *dev, + uint32_t privdef_en, + uint32_t hfnmi_en); + +/** + * \brief Disable MPU + * + * \param[in] dev MPU device \ref mpu_armv8m_dev_t + * + * \return Error code \ref mpu_armv8m_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpu_armv8m_error_t mpu_armv8m_disable(struct mpu_armv8m_dev_t *dev); + +/** + * \brief Disable MPU and clean all regions + * + * \param[in] dev MPU device \ref mpu_armv8m_dev_t + * + * \return Error code \ref mpu_armv8m_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpu_armv8m_error_t mpu_armv8m_clean(struct mpu_armv8m_dev_t *dev); + +/** + * \brief Enable MPU Region + * + * \param[in] dev MPU device \ref mpu_armv8m_dev_t + * \param[in] region_cfg MPU region config \ref mpu_armv8m_region_cfg_t + * + * \return Error code \ref mpu_armv8m_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpu_armv8m_error_t mpu_armv8m_region_enable( + struct mpu_armv8m_dev_t *dev, + struct mpu_armv8m_region_cfg_t *region_cfg); + +/** + * \brief Disable MPU Region + * + * \param[in] dev MPU device \ref mpu_armv8m_dev_t + * \param[in] region_nr Region number + * + * \return Error code \ref mpu_armv8m_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpu_armv8m_error_t mpu_armv8m_region_disable( + struct mpu_armv8m_dev_t *dev, + uint32_t region_nr); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPU_ARMV8M_DRV_H__ */ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/native_drivers/spu.c b/nrfdemo/build/tfm/api_ns/platform/common/core/native_drivers/spu.c new file mode 100644 index 0000000..3d93de8 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/native_drivers/spu.c @@ -0,0 +1,406 @@ +/* + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "spu.h" +#include "region_defs.h" +#include "array.h" + +/* Platform-specific configuration */ +#if NRF_SPU_HAS_MEMORY + +#define DEVICE_FLASH_BASE_ADDRESS FLASH_BASE_ADDRESS +#define DEVICE_SRAM_BASE_ADDRESS SRAM_BASE_ADDRESS + +#define FLASH_SECURE_ATTRIBUTION_REGION_SIZE SPU_FLASH_REGION_SIZE +#define SRAM_SECURE_ATTRIBUTION_REGION_SIZE SPU_SRAM_REGION_SIZE + +#define FLASH_SECURE_ATTRIBUTION_REGIONS_START_ID 0 +#define SRAM_SECURE_ATTRIBUTION_REGIONS_START_ID 64 + +#define NUM_FLASH_SECURE_ATTRIBUTION_REGIONS \ + (FLASH_TOTAL_SIZE / FLASH_SECURE_ATTRIBUTION_REGION_SIZE) +#define NUM_SRAM_SECURE_ATTRIBUTION_REGIONS \ + (TOTAL_RAM_SIZE / SRAM_SECURE_ATTRIBUTION_REGION_SIZE) + +/* Convenience macros for SPU Non-Secure Callable (NCS) attribution */ + +/* + * Determine the SPU Region number the given address belongs to. + * + * addr shall be a valid flash memory address + */ +#define FLASH_NSC_REGION_FROM_ADDR(addr) \ + ((uint32_t)addr / FLASH_SECURE_ATTRIBUTION_REGION_SIZE) + +/* + * Determine the NSC region size based on a given NCS region base address. + */ +#define FLASH_NSC_SIZE_FROM_ADDR(addr) (FLASH_SECURE_ATTRIBUTION_REGION_SIZE \ + - (((uint32_t)(addr)) % FLASH_SECURE_ATTRIBUTION_REGION_SIZE)) + +/* + * Determine the encoded the SPU NCS Region Size value, + * based on the absolute NCS region size in bytes. + * + * size shall be a valid SPU NCS Region size value + */ +#define FLASH_NSC_SIZE_REG(size) ((31 - __builtin_clz(size)) - 4) + +#if defined(REGION_PCD_SRAM_ADDRESS) +static bool spu_region_is_sram_region_in_address_range(uint8_t region_id, uint32_t start_address, uint32_t end_address) +{ + size_t start_id = (start_address - DEVICE_SRAM_BASE_ADDRESS) / SRAM_SECURE_ATTRIBUTION_REGION_SIZE; + size_t end_id = (end_address - DEVICE_SRAM_BASE_ADDRESS) / SRAM_SECURE_ATTRIBUTION_REGION_SIZE; + return region_id >= start_id && region_id <= end_id; +} +#endif + +static bool spu_region_is_pcd_region(NRF_SPU_Type * p_reg, uint8_t region_id) +{ + bool is_pcd = false; + +#ifdef PM_PCD_SRAM_ADDRESS + is_pcd = is_pcd || spu_region_is_sram_region_in_address_range(region_id, PM_PCD_SRAM_ADDRESS, PM_PCD_SRAM_END_ADDRESS); +#endif + + return is_pcd; +} + +#if defined(REGION_MCUBOOT_ADDRESS) || defined(REGION_B0_ADDRESS) || defined(REGION_S0_ADDRESS) || defined(REGION_S1_ADDRESS) +static bool spu_region_is_flash_region_in_address_range(uint8_t region_id, uint32_t start_address, uint32_t end_address) +{ + size_t start_id = (start_address - DEVICE_FLASH_BASE_ADDRESS) / FLASH_SECURE_ATTRIBUTION_REGION_SIZE; + size_t end_id = (end_address - DEVICE_FLASH_BASE_ADDRESS) / FLASH_SECURE_ATTRIBUTION_REGION_SIZE; + return region_id >= start_id && region_id <= end_id; +} +#endif + +static bool spu_region_is_bootloader_region(NRF_SPU_Type * p_reg, uint8_t region_id) +{ + bool is_bootloader = false; + +#ifdef REGION_MCUBOOT_ADDRESS + is_bootloader = is_bootloader || spu_region_is_flash_region_in_address_range(region_id, REGION_MCUBOOT_ADDRESS, REGION_MCUBOOT_END_ADDRESS); +#endif +#ifdef REGION_B0_ADDRESS + is_bootloader = is_bootloader || spu_region_is_flash_region_in_address_range(region_id, REGION_B0_ADDRESS, REGION_B0_END_ADDRESS); +#endif +#ifdef REGION_S0_ADDRESS + is_bootloader = is_bootloader || spu_region_is_flash_region_in_address_range(region_id, REGION_S0_ADDRESS, REGION_S0_END_ADDRESS); +#endif +#ifdef REGION_S1_ADDRESS + is_bootloader = is_bootloader || spu_region_is_flash_region_in_address_range(region_id, REGION_S1_ADDRESS, REGION_S1_END_ADDRESS); +#endif + + return is_bootloader; +} + +#endif /* NRF_SPU_HAS_MEMORY */ + +void spu_enable_interrupts(void) +{ + uint32_t mask = 0; + +#if NRF_SPU_HAS_MEMORY + mask |= NRF_SPU_INT_RAMACCERR_MASK; + mask |= NRF_SPU_INT_FLASHACCERR_MASK; +#endif + + mask |= NRF_SPU_INT_PERIPHACCERR_MASK; + + for(int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + nrf_spu_int_enable(spu_instances[i], mask); + } +} + +uint32_t spu_events_get(void) +{ + uint32_t events = 0; + + for(int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + if(nrf_spu_event_check(spu_instances[i], NRF_SPU_EVENT_PERIPHACCERR)){ + events |= SPU_EVENT_PERIPHACCERR; + } +#if NRF_SPU_HAS_MEMORY + if (nrf_spu_event_check(spu_instances[i], NRF_SPU_EVENT_RAMACCERR)) { + events |= SPU_EVENT_RAMACCERR; + } + if (nrf_spu_event_check(spu_instances[i], NRF_SPU_EVENT_FLASHACCERR)) { + events |= SPU_EVENT_FLASHACCERR; + } +#endif /* NRF_SPU_HAS_MEMORY */ + } + + return events; +} + +#ifdef MPC_PRESENT +void mpc_enable_interrupts(void) +{ + uint32_t mask = NRF_MPC_INT_MEMACCERR_MASK; + nrf_mpc_int_enable(NRF_MPC00, mask); +} + +uint32_t mpc_events_get(void) +{ + uint32_t events = 0; + + if (nrf_mpc_event_check(NRF_MPC00, NRF_MPC_EVENT_MEMACCERR)){ + events |= MPC_EVENT_MEMACCERR; + } + + return events; +} + +void mpc_clear_events() +{ + nrf_mpc_event_clear(NRF_MPC00, NRF_MPC_EVENT_MEMACCERR); +} +#endif /* MPC_PRESENT */ + +void spu_clear_events(void) +{ + for(int i = 0; i < ARRAY_SIZE(spu_instances); i++) { +#if NRF_SPU_HAS_MEMORY + nrf_spu_event_clear(spu_instances[i], NRF_SPU_EVENT_RAMACCERR); + nrf_spu_event_clear(spu_instances[i], NRF_SPU_EVENT_FLASHACCERR); +#endif + nrf_spu_event_clear(spu_instances[i], NRF_SPU_EVENT_PERIPHACCERR); + } +} + +#ifdef SPU_PERIPHACCERR_ADDRESS_ADDRESS_Msk +uint32_t spu_get_peri_addr(void) { + uint32_t addr = 0; + + for(int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + if(spu_instances[i]->EVENTS_PERIPHACCERR){ + /* Only the lower 16 bits of the address are captured into the register. The upper + * 16 bits correspond to the upper 16 bits of the SPU's base address. + */ + addr = spu_instances[i]->PERIPHACCERR.ADDRESS | ((uint32_t)spu_instances[i] & 0xFFFF0000); + } + } + + return addr; +} +#endif + +#if NRF_SPU_HAS_MEMORY +void spu_regions_reset_unlocked_secure(void) +{ + for (size_t i = 0; i < NUM_FLASH_SECURE_ATTRIBUTION_REGIONS ; i++) { + if (!spu_region_is_bootloader_region(NRF_SPU, i)) { + nrf_spu_flashregion_set(NRF_SPU, i, + SPU_SECURE_ATTR_SECURE, + NRF_SPU_MEM_PERM_READ + | NRF_SPU_MEM_PERM_WRITE + | NRF_SPU_MEM_PERM_EXECUTE, + SPU_LOCK_CONF_UNLOCKED); + } + } + + for (size_t i = 0; i < NUM_SRAM_SECURE_ATTRIBUTION_REGIONS ; i++) { + if (!spu_region_is_pcd_region(NRF_SPU, i)) { + nrf_spu_ramregion_set(NRF_SPU, i, + SPU_SECURE_ATTR_SECURE, + NRF_SPU_MEM_PERM_READ + | NRF_SPU_MEM_PERM_WRITE + | NRF_SPU_MEM_PERM_EXECUTE, + SPU_LOCK_CONF_UNLOCKED); + } + } +} + +void spu_regions_flash_config(uint32_t start_addr, uint32_t limit_addr, bool secure_attr, + uint32_t permissions, bool lock_conf) +{ + /* Determine start and last flash region number */ + size_t start_id = + (start_addr - DEVICE_FLASH_BASE_ADDRESS) / + FLASH_SECURE_ATTRIBUTION_REGION_SIZE; + size_t last_id = + (limit_addr - DEVICE_FLASH_BASE_ADDRESS) / + FLASH_SECURE_ATTRIBUTION_REGION_SIZE; + + /* Configure all flash regions between start_id and last_id */ + for (size_t i = start_id; i <= last_id; i++) { + nrf_spu_flashregion_set(NRF_SPU, i, secure_attr, permissions, lock_conf); + } +} + +void spu_regions_sram_config(uint32_t start_addr, uint32_t limit_addr, bool secure_attr, + uint32_t permissions, bool lock_conf) +{ + /* Determine start and last ram region number */ + size_t start_id = + (start_addr - DEVICE_SRAM_BASE_ADDRESS) / + SRAM_SECURE_ATTRIBUTION_REGION_SIZE; + size_t last_id = + (limit_addr - DEVICE_SRAM_BASE_ADDRESS) / + SRAM_SECURE_ATTRIBUTION_REGION_SIZE; + + /* Configure all ram regions between start_id and last_id */ + for (size_t i = start_id; i <= last_id; i++) { + nrf_spu_ramregion_set(NRF_SPU, i, secure_attr, permissions, lock_conf); + } +} + +void spu_regions_flash_config_non_secure_callable(uint32_t start_addr, + uint32_t limit_addr) +{ + size_t size = limit_addr - start_addr + 1; + + uint32_t nsc_size = FLASH_NSC_SIZE_FROM_ADDR(start_addr); + + /* Check Non-Secure Callable region possible overflow */ + NRFX_ASSERT(size <= nsc_size); + + /* Check Non-Secure Callable region ending on SPU boundary */ + NRFX_ASSERT(((start_addr + nsc_size) % + FLASH_SECURE_ATTRIBUTION_REGION_SIZE) == 0); + + /* Check Non-Secure Callable region power-of-2 size compliance */ + NRFX_ASSERT((nsc_size & (nsc_size - 1)) == 0); + + /* Check Non-Secure Callable region size is within [32, 4096] range */ + NRFX_ASSERT((nsc_size >= 32) && (nsc_size <= 4096)); + + nrf_spu_flashnsc_set(NRF_SPU, 0, + FLASH_NSC_SIZE_REG(nsc_size), + FLASH_NSC_REGION_FROM_ADDR(start_addr), + SPU_LOCK_CONF_LOCKED); +} + +uint32_t spu_regions_flash_get_base_address_in_region(uint32_t region_id) +{ + return FLASH_BASE_ADDRESS + + ((region_id - FLASH_SECURE_ATTRIBUTION_REGIONS_START_ID) * + FLASH_SECURE_ATTRIBUTION_REGION_SIZE); +} + +uint32_t spu_regions_flash_get_last_address_in_region(uint32_t region_id) +{ + return FLASH_BASE_ADDRESS + + ((region_id - FLASH_SECURE_ATTRIBUTION_REGIONS_START_ID + 1) * + FLASH_SECURE_ATTRIBUTION_REGION_SIZE) - 1; +} + +uint32_t spu_regions_flash_get_start_id(void) { + + return FLASH_SECURE_ATTRIBUTION_REGIONS_START_ID; +} + +uint32_t spu_regions_flash_get_last_id(void) { + + return FLASH_SECURE_ATTRIBUTION_REGIONS_START_ID + + NUM_FLASH_SECURE_ATTRIBUTION_REGIONS - 1; +} + +uint32_t spu_regions_flash_get_region_size(void) { + + return FLASH_SECURE_ATTRIBUTION_REGION_SIZE; +} + +uint32_t spu_regions_sram_get_base_address_in_region(uint32_t region_id) +{ + return SRAM_BASE_ADDRESS + + ((region_id - SRAM_SECURE_ATTRIBUTION_REGIONS_START_ID) * + SRAM_SECURE_ATTRIBUTION_REGION_SIZE); +} + +uint32_t spu_regions_sram_get_last_address_in_region(uint32_t region_id) +{ + return SRAM_BASE_ADDRESS + + ((region_id - SRAM_SECURE_ATTRIBUTION_REGIONS_START_ID + 1) * + SRAM_SECURE_ATTRIBUTION_REGION_SIZE) - 1; +} + +uint32_t spu_regions_sram_get_start_id(void) { + + return SRAM_SECURE_ATTRIBUTION_REGIONS_START_ID; +} + +uint32_t spu_regions_sram_get_last_id(void) { + + return SRAM_SECURE_ATTRIBUTION_REGIONS_START_ID + + NUM_SRAM_SECURE_ATTRIBUTION_REGIONS - 1; +} + +uint32_t spu_regions_sram_get_region_size(void) { + + return SRAM_SECURE_ATTRIBUTION_REGION_SIZE; +} + +#endif /* NRF_SPU_HAS_MEMORY */ + +void spu_peripheral_config_secure(const uint32_t periph_base_address, bool periph_lock) +{ + uint8_t periph_id = NRFX_PERIPHERAL_ID_GET(periph_base_address); + +#if NRF_SPU_HAS_MEMORY + /* ASSERT checking that this is not an explicit Non-Secure peripheral */ + NRFX_ASSERT((NRF_SPU->PERIPHID[periph_id].PERM & + SPU_PERIPHID_PERM_SECUREMAPPING_Msk) != + (SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure << + SPU_PERIPHID_PERM_SECUREMAPPING_Pos)); + + nrf_spu_peripheral_set(NRF_SPU, periph_id, + 1 /* Secure */, + 1 /* Secure DMA */, + periph_lock); + +#else + + NRF_SPU_Type * nrf_spu = spu_instance_from_peripheral_addr(periph_base_address); + + uint8_t spu_id = NRFX_PERIPHERAL_ID_GET(nrf_spu); + + uint8_t index = periph_id - spu_id; + + nrf_spu_periph_perm_secattr_set(nrf_spu, index, true /* Secure */); + nrf_spu_periph_perm_dmasec_set(nrf_spu, index, true /* Secure */); + nrf_spu_periph_perm_lock_enable(nrf_spu, index); +#endif +} + +void spu_peripheral_config_non_secure(const uint32_t periph_base_address, bool periph_lock) +{ + uint8_t periph_id = NRFX_PERIPHERAL_ID_GET(periph_base_address); + +#if NRF_SPU_HAS_MEMORY + /* ASSERT checking that this is not an explicit Secure peripheral */ + NRFX_ASSERT((NRF_SPU->PERIPHID[periph_id].PERM & + SPU_PERIPHID_PERM_SECUREMAPPING_Msk) != + (SPU_PERIPHID_PERM_SECUREMAPPING_Secure << + SPU_PERIPHID_PERM_SECUREMAPPING_Pos)); + + nrf_spu_peripheral_set(NRF_SPU, periph_id, + 0 /* Non-Secure */, + 0 /* Non-Secure DMA */, + periph_lock); +#else + NRF_SPU_Type * nrf_spu = spu_instance_from_peripheral_addr(periph_base_address); + + uint8_t spu_id = NRFX_PERIPHERAL_ID_GET(nrf_spu); + + uint8_t index = periph_id - spu_id; + + nrf_spu_periph_perm_secattr_set(nrf_spu, index, false /* Non-Secure */); + nrf_spu_periph_perm_dmasec_set(nrf_spu, index, false /* Non-Secure */); + nrf_spu_periph_perm_lock_enable(nrf_spu, index); +#endif +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/native_drivers/spu.h b/nrfdemo/build/tfm/api_ns/platform/common/core/native_drivers/spu.h new file mode 100644 index 0000000..8c8856a --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/native_drivers/spu.h @@ -0,0 +1,272 @@ +/* + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SPU_H__ +#define __SPU_H__ + +#include <stddef.h> +#include <stdint.h> +#include <stdbool.h> +#include <nrfx.h> + +#include <hal/nrf_spu.h> +#ifdef MPC_PRESENT +#include <hal/nrf_mpc.h> +#endif + +#define SPU_LOCK_CONF_LOCKED true +#define SPU_LOCK_CONF_UNLOCKED false +#define SPU_SECURE_ATTR_SECURE true +#define SPU_SECURE_ATTR_NONSECURE false + +__attribute__((unused)) static NRF_SPU_Type * spu_instances[] = { +#ifdef NRF_SPU + NRF_SPU, +#endif +#ifdef NRF_SPU00 + NRF_SPU00, +#endif +#ifdef NRF_SPU10 + NRF_SPU10, +#endif +#ifdef NRF_SPU20 + NRF_SPU20, +#endif +#ifdef NRF_SPU30 + NRF_SPU30, +#endif +}; + +/** + * \brief SPU interrupt enabling + * + * Enable security violations outside the Cortex-M33 + * to trigger SPU interrupts. + */ +void spu_enable_interrupts(void); + +enum spu_events { + SPU_EVENT_RAMACCERR = 1 << 0, + SPU_EVENT_FLASHACCERR = 1 << 1, + SPU_EVENT_PERIPHACCERR= 1 << 2, + MPC_EVENT_MEMACCERR = 1 << 3 +}; + +/** + * \brief Retrieve bitmask of SPU events. + */ +uint32_t spu_events_get(void); + +/** + * \brief SPU event clearing + * + * Clear SPU event registers + */ +void spu_clear_events(void); + +/** + * \brief Reset TF-M memory regions to being Secure. + * + * Reset all (Flash or SRAM, but excluding the regions owned by the + * bootloader(s)) memory region permissions to be Secure and have the + * default (Read-Write-Execute allow) access policy. + * + * \note region lock is not applied to allow modifying the configuration. + */ +void spu_regions_reset_unlocked_secure(void); + +/** + * \brief Configure the SPU Flash memory region + */ +void spu_regions_flash_config(uint32_t start_addr, uint32_t limit_addr, bool secure_attr, + uint32_t permissions, bool lock_conf); + +/** + * \brief Configure SPU SRAM memory regions + */ +void spu_regions_sram_config(uint32_t start_addr, uint32_t limit_addr, bool secure_attr, + uint32_t permissions, bool lock_conf); + +/** + * \brief Configure Non-Secure Callable area + * + * Configure a single region in Secure Flash as Non-Secure Callable + * (NSC) area. + * + * \note Any Secure Entry functions, exposing secure services to the + * Non-Secure firmware, shall be located inside this NSC area. + * + * If the start address of the NSC area is hard-coded, it must follow + * the HW restrictions: The size must be a power of 2 between 32 and + * 4096, and the end address must fall on a SPU region boundary. + * + * \note region lock is applied to prevent further modification during + * the current reset cycle. + */ +void spu_regions_flash_config_non_secure_callable(uint32_t start_addr, uint32_t limit_addr); + +/** + * \brief Restrict access to peripheral to secure + * + * Configure a device peripheral to be accessible from Secure domain only. + * + * \param periph_base_address Base address of a particular peripheral. + * \param periph_lock Variable indicating whether to lock peripheral security + * + * \note + * - peripheral shall not be a Non-Secure only peripheral + * - DMA transactions are configured as Secure + */ +void spu_peripheral_config_secure(const uint32_t periph_base_address, bool periph_lock); + +/** + * Configure a device peripheral to be accessible from Non-Secure domain. + * + * \param periph_base_address Base address of a particular peripheral. + * \param periph_lock Variable indicating whether to lock peripheral security + * + * \note + * - peripheral shall not be a Secure-only peripheral + * - DMA transactions are configured as Non-Secure + */ +void spu_peripheral_config_non_secure(const uint32_t periph_base_address, bool periph_lock); + +/** + * /brief Retrieve the address of the transaction that triggered PERIPHACCERR. + * + */ +uint32_t spu_get_peri_addr(void); + +/** + * Return the SPU instance that can be used to configure the + * peripheral at the given base address. + */ +static inline NRF_SPU_Type * spu_instance_from_peripheral_addr(uint32_t peripheral_addr) +{ + /* See the SPU chapter in the IPS for how this is calculated */ + + uint32_t apb_bus_number = peripheral_addr & 0x00FC0000; + + return (NRF_SPU_Type *)(0x50000000 | apb_bus_number); +} + +/** + * \brief Return base address of a Flash SPU regions + * + * Get the base (lowest) address of a particular Flash SPU region + * + * \param region_id Valid flash SPU region ID + * + * \return the base address of the given flash SPU region + */ +uint32_t spu_regions_flash_get_base_address_in_region(uint32_t region_id); + +/** + * \brief Return last address of a Flash SPU regions + * + * Get the last (highest) address of a particular Flash SPU region + * + * \param region_id Valid flash SPU region ID + * + * \return the last address of the given flash SPU region + */ +uint32_t spu_regions_flash_get_last_address_in_region(uint32_t region_id); + +/** + * \brief Return the ID of the first Flash SPU region + * + * \return the first Flash region ID + */ +uint32_t spu_regions_flash_get_start_id(void); + +/** + * \brief Return the ID of the last Flash SPU region + * + * \return the last Flash region ID + */ +uint32_t spu_regions_flash_get_last_id(void); + +/** + * \brief Return the size of Flash SPU regions + * + * \return the size of Flash SPU regions + */ +uint32_t spu_regions_flash_get_region_size(void); + +/** + * \brief Return base address of a SRAM SPU regions + * + * Get the base (lowest) address of a particular SRAM SPU region + * + * \param region_id Valid SRAM SPU region ID + * + * \return the base address of the given SRAM SPU region + */ +uint32_t spu_regions_sram_get_base_address_in_region(uint32_t region_id); + +/** + * \brief Return last address of a SRAM SPU regions + * + * Get the last (highest) address of a particular SRAM SPU region + * + * \param region_id Valid SRAM SPU region ID + * + * \return the last address of the given SRAM SPU region + */ +uint32_t spu_regions_sram_get_last_address_in_region(uint32_t region_id); + +/** + * \brief Return the ID of the first SRAM SPU region + * + * \return the first SRAM region ID + */ +uint32_t spu_regions_sram_get_start_id(void); + +/** + * \brief Return the ID of the last SRAM SPU region + * + * \return the last SRAM region ID + */ +uint32_t spu_regions_sram_get_last_id(void); + +/** + * \brief Return the size of SRAM SPU regions + * + * \return the size of SRAM SPU regions + */ +uint32_t spu_regions_sram_get_region_size(void); + +/** + * \brief MPC interrupt enabling + * + * Enable security violations outside the Cortex-M33 + * to trigger SPU interrupts. + */ +void mpc_enable_interrupts(void); + +/** + * \brief Retrieve bitmask of MPC events. + */ +uint32_t mpc_events_get(void); + +/** + * \brief MPC event clearing + * + * Clear MPC event registers + */ +void mpc_clear_events(void); + +#endif diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/nrfx/nrfx.h b/nrfdemo/build/tfm/api_ns/platform/common/core/nrfx/nrfx.h new file mode 100644 index 0000000..9783e11 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/nrfx/nrfx.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_H__ +#define NRFX_H__ + +#include <nrfx_config.h> +#include <drivers/nrfx_common.h> +#include <nrfx_glue.h> +#include <hal/nrf_common.h> +#include <drivers/nrfx_errors.h> + +#endif // NRFX_H__ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/nrfx_config.h b/nrfdemo/build/tfm/api_ns/platform/common/core/nrfx_config.h new file mode 100644 index 0000000..f76e49c --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/nrfx_config.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_CONFIG_H__ +#define NRFX_CONFIG_H__ + +#include <RTE_Device.h> + +#if RTE_FLASH0 + +#include <nrf.h> + +#if defined(NRF_NVMC_S) +#define NRFX_NVMC_ENABLED 1 +#elif defined(NRF_RRAMC_S) +#define NRFX_RRAMC_ENABLED 1 +#else +#error "Unrecognized platform" +#endif + +#endif /* RTE_FLASH0 */ + +#if RTE_USART0 || RTE_USART1 || RTE_USART2 || RTE_USART3 || \ + RTE_USART00 || RTE_USART20 || RTE_USART21 || RTE_USART22 || RTE_USART30 +#define NRFX_UARTE_ENABLED 1 +#endif +#if RTE_USART0 +#define NRFX_UARTE0_ENABLED 1 +#endif +#if RTE_USART1 +#define NRFX_UARTE1_ENABLED 1 +#endif +#if RTE_USART2 +#define NRFX_UARTE2_ENABLED 1 +#endif +#if RTE_USART3 +#define NRFX_UARTE3_ENABLED 1 +#endif + +/* 54L15 has different UART instances */ +#if RTE_USART00 +#define NRFX_UARTE00_ENABLED 1 +#endif +#if RTE_USART20 +#define NRFX_UARTE20_ENABLED 1 +#endif +#if RTE_USART21 +#define NRFX_UARTE21_ENABLED 1 +#endif +#if RTE_USART22 +#define NRFX_UARTE22_ENABLED 1 +#endif +#if RTE_USART30 +#define NRFX_UARTE30_ENABLED 1 +#endif + +/* + * For chips with TrustZone support, MDK provides CMSIS-Core peripheral + * accessing symbols in two flavors, with secure and non-secure base address + * mappings. Their names contain the suffix _S or _NS, respectively. + * Because nrfx HALs and drivers require these peripheral accessing symbols + * without any suffixes, the following macro is provided that will translate + * their names according to the kind of the target that is built. + */ +#if defined(NRF_TRUSTZONE_NONSECURE) +#define NRF_PERIPH(P) P##_NS +#else +#define NRF_PERIPH(P) P##_S +#endif + +#if defined(NRF5340_XXAA_APPLICATION) + #include <nrfx_config_nrf5340_application.h> +#elif defined(NRF91_SERIES) + #include <nrfx_config_nrf91.h> +#elif defined(NRF54L15_ENGA_XXAA) + #include <nrfx_config_nrf54l15_application.h> +#else + #error "Unknown device." +#endif + +#endif // NRFX_CONFIG_H__ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/nrfx_glue.c b/nrfdemo/build/tfm/api_ns/platform/common/core/nrfx_glue.c new file mode 100644 index 0000000..df2b590 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/nrfx_glue.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <nrfx.h> + +static uint32_t in_critical_section; + +void nrfx_critical_section_enter(void) +{ + __disable_irq(); + ++in_critical_section; +} + +void nrfx_critical_section_exit(void) +{ + NRFX_ASSERT(in_critical_section > 0); + + --in_critical_section; + if (in_critical_section == 0) + { + __enable_irq(); + } +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/pal_plat_test.c b/nrfdemo/build/tfm/api_ns/platform/common/core/pal_plat_test.c new file mode 100644 index 0000000..01122d9 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/pal_plat_test.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2022 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include <string.h> +#include "tfm_plat_test.h" +#include "pal_plat_test.h" +#include <stdint.h> +#include <stdbool.h> +#include <helpers/nrfx_reset_reason.h> +#include <region_defs.h> + +uint32_t pal_nvmem_get_addr(void) +{ +#ifdef NRF_TRUSTZONE_NONSECURE + static bool psa_scratch_initialized = false; + + if (!psa_scratch_initialized) { + uint32_t reset_reason = nrfx_reset_reason_get(); + nrfx_reset_reason_clear(reset_reason); + + int is_pinreset = reset_reason & NRFX_RESET_REASON_RESETPIN_MASK; + if ((reset_reason == 0) || is_pinreset){ + /* PSA API tests expect this area to be initialized to all 0xFFs + * after a power-on or pin reset. + */ + memset((void*)PSA_TEST_SCRATCH_AREA_BASE, 0xFF, PSA_TEST_SCRATCH_AREA_SIZE); + } + psa_scratch_initialized = true; + } +#endif /* NRF_TRUSTZONE_NONSECURE */ + return (uint32_t)PSA_TEST_SCRATCH_AREA_BASE; +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/pal_plat_test.h b/nrfdemo/build/tfm/api_ns/platform/common/core/pal_plat_test.h new file mode 100644 index 0000000..2a63251 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/pal_plat_test.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \note These interfaces are needed to execute PSA tests + * on Nordic platforms + */ + +/** + * \brief Get the address of a free, word-aligned, 1K memory area. + */ +uint32_t pal_nvmem_get_addr(void); diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/services/include/tfm_ioctl_core_api.h b/nrfdemo/build/tfm/api_ns/platform/common/core/services/include/tfm_ioctl_core_api.h new file mode 100644 index 0000000..df3c8d6 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/services/include/tfm_ioctl_core_api.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** @file + * @brief TFM IOCTL API header. + */ + + +#ifndef TFM_IOCTL_CORE_API_H__ +#define TFM_IOCTL_CORE_API_H__ + +/** + * @defgroup tfm_ioctl_api TFM IOCTL API + * @{ + * + */ + +#include <limits.h> +#include <tfm_platform_api.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Supported request types. + */ +enum tfm_platform_ioctl_core_reqest_types_t { + TFM_PLATFORM_IOCTL_READ_SERVICE, + TFM_PLATFORM_IOCTL_GPIO_SERVICE, + + /* Last core service, start platform specific from this value. */ + TFM_PLATFORM_IOCTL_CORE_LAST +}; + +/** @brief Argument list for each platform read service. + */ +struct tfm_read_service_args_t { + void *destination; + uint32_t addr; + size_t len; +}; + + +/** @brief Output list for each read platform service + */ +struct tfm_read_service_out_t { + uint32_t result; +}; + +enum tfm_gpio_service_type { + /** Select which MCU / Subsystem controls the pin */ + TFM_GPIO_SERVICE_TYPE_PIN_MCU_SELECT = 0, +}; + +/** @brief Arguments for selecting the MCU to control a GPIO pin. */ +struct tfm_gpio_service_args_mcu_select { + uint32_t pin_number; + uint32_t mcu; +}; + +/** @brief Argument list for each platform GPIO service */ +struct tfm_gpio_service_args { + uint32_t type; + union { + struct tfm_gpio_service_args_mcu_select mcu_select; + }; +}; + +/** @brief Output list for each GPIO platform service + */ +struct tfm_gpio_service_out { + uint32_t result; +}; + +/** + * @brief Perform a read operation. + * + * @param[out] destination Pointer where read result is stored + * @param[in] addr Address to read from + * @param[in] len Number of bytes to read + * @param[out] result Result of operation + * + * @return Returns values as specified by the tfm_platform_err_t + */ +enum tfm_platform_err_t tfm_platform_mem_read(void *destination, uint32_t addr, + size_t len, uint32_t *result); + +/** @brief Represents an accepted read range. + */ +struct tfm_read_service_range { + uint32_t start; + size_t size; +}; + +/** + * @brief Perform a GPIO MCU select operation. + * + * @param pin_number Pin_number. + * @param mcu MCU to control the pin, use nrf_gpio_pin_sel_t values. + + * @param[out] result Result of operation + * + * @return Returns values as specified by the tfm_platform_err_t + */ +enum tfm_platform_err_t tfm_platform_gpio_pin_mcu_select(uint32_t pin_number, uint32_t mcu, + uint32_t *result); + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* TFM_IOCTL_CORE_API_H__ */ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/services/include/tfm_platform_hal_ioctl.h b/nrfdemo/build/tfm/api_ns/platform/common/core/services/include/tfm_platform_hal_ioctl.h new file mode 100644 index 0000000..abe940b --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/services/include/tfm_platform_hal_ioctl.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** @file + * @brief TFM IOCTL API header. + */ + + +#ifndef TFM_PLATFORM_HAL_IOCTL_H__ +#define TFM_PLATFORM_HAL_IOCTL_H__ + +#include "psa/client.h" +#include "tfm_plat_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum tfm_platform_err_t +tfm_platform_hal_read_service(const psa_invec *in_vec, + const psa_outvec *out_vec); + +enum tfm_platform_err_t +tfm_platform_hal_gpio_service(const psa_invec *in_vec, const psa_outvec *out_vec); + +#ifdef __cplusplus +} +#endif + +#endif /* TFM_IOCTL_API_H__ */ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/services/src/tfm_ioctl_core_ns_api.c b/nrfdemo/build/tfm/api_ns/platform/common/core/services/src/tfm_ioctl_core_ns_api.c new file mode 100644 index 0000000..2370988 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/services/src/tfm_ioctl_core_ns_api.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "nrf.h" +#include <stdint.h> +#include <tfm_platform_api.h> +#include <tfm_ioctl_core_api.h> + +enum tfm_platform_err_t tfm_platform_mem_read(void *destination, uint32_t addr, + size_t len, uint32_t *result) +{ + enum tfm_platform_err_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_read_service_args_t args; + struct tfm_read_service_out_t out; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)&out; + out_vec.len = sizeof(out); + + args.destination = destination; + args.addr = addr; + args.len = len; + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_READ_SERVICE, &in_vec, + &out_vec); + + *result = out.result; + + return ret; +} + +enum tfm_platform_err_t tfm_platform_gpio_pin_mcu_select(uint32_t pin_number, uint32_t mcu, + uint32_t *result) +{ +#if defined(GPIO_PIN_CNF_MCUSEL_Msk) + enum tfm_platform_err_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_gpio_service_args args; + struct tfm_gpio_service_out out; + + args.type = TFM_GPIO_SERVICE_TYPE_PIN_MCU_SELECT; + args.mcu_select.pin_number = pin_number; + args.mcu_select.mcu = mcu; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)&out; + out_vec.len = sizeof(out); + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_GPIO_SERVICE, &in_vec, + &out_vec); + + *result = out.result; + + return ret; +#else + return TFM_PLATFORM_ERR_NOT_SUPPORTED; +#endif +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/services/src/tfm_ioctl_core_s_api.c b/nrfdemo/build/tfm/api_ns/platform/common/core/services/src/tfm_ioctl_core_s_api.c new file mode 100644 index 0000000..479a0fe --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/services/src/tfm_ioctl_core_s_api.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#include "nrf.h" +#include <stdint.h> +#include "tfm_platform_api.h" +#include "tfm_ioctl_core_api.h" + +__attribute__((section("SFN"))) +enum tfm_platform_err_t tfm_platform_mem_read(void *destination, uint32_t addr, + size_t len, uint32_t *result) +{ + psa_status_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_read_service_args_t args; + struct tfm_read_service_out_t out; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)&out; + out_vec.len = sizeof(out); + + args.destination = destination; + args.addr = addr; + args.len = len; + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_READ_SERVICE, &in_vec, + &out_vec); + + return (enum tfm_platform_err_t) ret; +} + +__attribute__((section("SFN"))) +enum tfm_platform_err_t tfm_platform_gpio_pin_mcu_select(uint32_t pin_number, uint32_t mcu, + uint32_t *result) +{ +#if defined(GPIO_PIN_CNF_MCUSEL_Msk) + enum tfm_platform_err_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_gpio_service_args args; + struct tfm_gpio_service_out out; + + args.type = TFM_GPIO_SERVICE_TYPE_PIN_MCU_SELECT; + args.mcu_select.pin_number = pin_number; + args.mcu_select.mcu = mcu; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)&out; + out_vec.len = sizeof(out); + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_GPIO_SERVICE, &in_vec, + &out_vec); + + *result = out.result; + + return ret; +#else + return TFM_PLATFORM_ERR_NOT_SUPPORTED; +#endif +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/services/src/tfm_platform_hal_ioctl.c b/nrfdemo/build/tfm/api_ns/platform/common/core/services/src/tfm_platform_hal_ioctl.c new file mode 100644 index 0000000..c916f4e --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/services/src/tfm_platform_hal_ioctl.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2021-2022 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <platform/include/tfm_platform_system.h> +#include <cmsis.h> +#include <stdio.h> +#include <tfm_ioctl_core_api.h> +#include <string.h> +#include <arm_cmse.h> +#include <array.h> +#include <tfm_hal_isolation.h> + +/* This contains the user provided allowed ranges */ +#include <tfm_read_ranges.h> + +#include <hal/nrf_gpio.h> + +#include "handle_attr.h" + +enum tfm_platform_err_t +tfm_platform_hal_read_service(const psa_invec *in_vec, + const psa_outvec *out_vec) +{ + struct tfm_read_service_args_t *args; + struct tfm_read_service_out_t *out; + enum tfm_hal_status_t status; + enum tfm_platform_err_t err; + uintptr_t boundary = (1 << HANDLE_ATTR_NS_POS) & + HANDLE_ATTR_NS_MASK; + uint32_t attr = TFM_HAL_ACCESS_READWRITE; + + if (in_vec->len != sizeof(struct tfm_read_service_args_t) || + out_vec->len != sizeof(struct tfm_read_service_out_t)) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + args = (struct tfm_read_service_args_t *)in_vec->base; + out = (struct tfm_read_service_out_t *)out_vec->base; + + /* Assume failure, unless valid region is hit in the loop */ + out->result = -1; + err = TFM_PLATFORM_ERR_INVALID_PARAM; + + if (args->destination == NULL || args->len <= 0) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + status = tfm_hal_memory_check(boundary, (uintptr_t)args->destination, + args->len, attr); + if (status != TFM_HAL_SUCCESS) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + for (size_t i = 0; i < ARRAY_SIZE(ranges); i++) { + uint32_t start = ranges[i].start; + uint32_t size = ranges[i].size; + + if (args->addr >= start && + args->addr + args->len <= start + size) { + memcpy(args->destination, + (const void *)args->addr, + args->len); + out->result = 0; + err = TFM_PLATFORM_ERR_SUCCESS; + break; + } + } + + return err; +} + +#if NRF_GPIO_HAS_SEL +static bool valid_mcu_select(uint32_t mcu) +{ + switch (mcu) { +#if defined(NRF54L15_ENGA_XXAA) + case NRF_GPIO_PIN_SEL_GPIO: + case NRF_GPIO_PIN_SEL_VPR: + case NRF_GPIO_PIN_SEL_GRTC: + case NRF_GPIO_PIN_SEL_TND: +#else + case NRF_GPIO_PIN_SEL_APP: + case NRF_GPIO_PIN_SEL_NETWORK: + case NRF_GPIO_PIN_SEL_PERIPHERAL: + case NRF_GPIO_PIN_SEL_TND: +#endif + return true; + default: + return false; + } +} + +static uint32_t gpio_service_mcu_select(struct tfm_gpio_service_args * args) +{ + if (nrf_gpio_pin_present_check(args->mcu_select.pin_number) && + valid_mcu_select(args->mcu_select.mcu)) { + nrf_gpio_pin_control_select(args->mcu_select.pin_number, args->mcu_select.mcu); + return 0; + } else { + return -1; + } +} + +enum tfm_platform_err_t +tfm_platform_hal_gpio_service(const psa_invec *in_vec, const psa_outvec *out_vec) +{ + struct tfm_gpio_service_args *args; + struct tfm_gpio_service_out *out; + + if (in_vec->len != sizeof(struct tfm_gpio_service_args) || + out_vec->len != sizeof(struct tfm_gpio_service_out)) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + args = (struct tfm_gpio_service_args *)in_vec->base; + out = (struct tfm_gpio_service_out *)out_vec->base; + out->result = -1; + + switch(args->type) + { + case TFM_GPIO_SERVICE_TYPE_PIN_MCU_SELECT: + out->result = gpio_service_mcu_select(args); + break; + default: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } + + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif /* NRF_GPIO_HAS_SEL */ + diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/startup.c b/nrfdemo/build/tfm/api_ns/platform/common/core/startup.c new file mode 100644 index 0000000..84f0af0 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/startup.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "cmsis.h" + +#ifdef NRF_HW_INIT_RESET_ON_BOOT +#include "hw_init.h" +#endif + +#include "startup.h" + +#if !(defined(DOMAIN_NS) || defined(BL2)) +#include "utilities.h" +#endif + +void default_irq_handler(void) +{ + /* + * This file is used by the TF-M build system. Usually in the + * secure domain (tfm_s.elf), but also for vanilla BL2 and for + * testing purposes in the non-secure domain (tfm_ns.elf). + * + * When used in vanilla BL2 or the non-secure domain we do not + * have tfm_core_panic so we loop forever instead. + */ +#if defined(DOMAIN_NS) || defined(BL2) + while(1); +#else + tfm_core_panic(); +#endif +} + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __disable_irq(); +#ifdef NRF_HW_INIT_RESET_ON_BOOT + /* Reset CONTROL register */ + __set_CONTROL(0); + + /* Allow the MSP and PSP stacks to descend to address 0, + * effectively disabling stack overflow protection. + */ + __set_MSPLIM(0); + __set_PSPLIM(0); + + /* Disable MPU */ + ARM_MPU_Disable(); +#endif /* NRF_HW_INIT_RESET_ON_BOOT */ + + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); + +#ifdef NRF_HW_INIT_RESET_ON_BOOT + /* Initialize core architecture registers and system blocks */ + hw_init_reset_on_boot(); +#endif /* NRF_HW_INIT_RESET_ON_BOOT */ +#endif + + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/startup.h b/nrfdemo/build/tfm/api_ns/platform/common/core/startup.h new file mode 100644 index 0000000..3906f13 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/startup.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * This file has declarations needed by startup.c and + * startup_<platform>.c. + */ + +#ifndef __STARTUP_H__ +#define __STARTUP_H__ + +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +typedef void(*VECTOR_TABLE_Type)(void); + +void __PROGRAM_START(void) __NO_RETURN; + +#define DEFAULT_IRQ_HANDLER(handler_name) \ +__NO_RETURN void __attribute__((weak, alias("default_tfm_IRQHandler"))) handler_name(void); + +__NO_RETURN void Reset_Handler(void); +__NO_RETURN void HardFault_Handler(void); +__NO_RETURN void MemManage_Handler(void); +__NO_RETURN void BusFault_Handler(void); +__NO_RETURN void UsageFault_Handler(void); +__NO_RETURN void SecureFault_Handler(void); + +void SPU_IRQHandler(void); + +void SPU00_IRQHandler(void); +void SPU10_IRQHandler(void); +void SPU20_IRQHandler(void); +void SPU30_IRQHandler(void); + +void MPC00_IRQHandler(void); + +void CRACEN_IRQHandler(void); + +/* + * The default irq handler is used as a backup in case of + * misconfiguration. + */ +void default_irq_handler(void); + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + +#endif /* __STARTUP_H__ */ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/startup_nrf91.c b/nrfdemo/build/tfm/api_ns/platform/common/core/startup_nrf91.c new file mode 100644 index 0000000..d82f6a6 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/startup_nrf91.c @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "cmsis.h" +#include "startup.h" +#include "exception_info.h" + +__NO_RETURN __attribute__((naked)) void default_tfm_IRQHandler(void) { + EXCEPTION_INFO(); + + __ASM volatile( + "BL default_irq_handler \n" + "B . \n" + ); +} + +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(CLOCK_POWER_IRQHandler) +DEFAULT_IRQ_HANDLER(UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler) +DEFAULT_IRQ_HANDLER(UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler) +DEFAULT_IRQ_HANDLER(UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler) +DEFAULT_IRQ_HANDLER(UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler) +DEFAULT_IRQ_HANDLER(GPIOTE0_IRQHandler) +DEFAULT_IRQ_HANDLER(SAADC_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER0_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER1_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER2_IRQHandler) +DEFAULT_IRQ_HANDLER(RTC0_IRQHandler) +DEFAULT_IRQ_HANDLER(RTC1_IRQHandler) +DEFAULT_IRQ_HANDLER(WDT_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU0_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU1_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU2_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU3_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU4_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU5_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM0_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM1_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM2_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM3_IRQHandler) +DEFAULT_IRQ_HANDLER(PDM_IRQHandler) +DEFAULT_IRQ_HANDLER(I2S_IRQHandler) +DEFAULT_IRQ_HANDLER(IPC_IRQHandler) +DEFAULT_IRQ_HANDLER(FPU_IRQHandler) +DEFAULT_IRQ_HANDLER(GPIOTE1_IRQHandler) +DEFAULT_IRQ_HANDLER(KMU_IRQHandler) +DEFAULT_IRQ_HANDLER(CRYPTOCELL_IRQHandler) + +#if defined(DOMAIN_NS) || defined(BL2) +DEFAULT_IRQ_HANDLER(SPU_IRQHandler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +#else +/* + * Default IRQ handlers will usually be overriden as they are + * weak. But due to the way TF-M links it's binary (doesn't use + * whole-archive), weak doesn't always work. So we explicitly ifdef + * out some IRQ handlers that we know will be overridden anyway to be + * safe. + */ +#endif + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + SecureFault_Handler, /* Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + + /* External Interrupts */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SPU_IRQHandler, + 0, /* Reserved */ + CLOCK_POWER_IRQHandler, + 0, /* Reserved */ + 0, /* Reserved */ + UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler, + UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler, + UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler, + UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler, + 0, /* Reserved */ + GPIOTE0_IRQHandler, + SAADC_IRQHandler, + TIMER0_IRQHandler, + TIMER1_IRQHandler, + TIMER2_IRQHandler, + 0, /* Reserved */ + 0, /* Reserved */ + RTC0_IRQHandler, + RTC1_IRQHandler, + 0, /* Reserved */ + 0, /* Reserved */ + WDT_IRQHandler, + 0, /* Reserved */ + 0, /* Reserved */ + EGU0_IRQHandler, + EGU1_IRQHandler, + EGU2_IRQHandler, + EGU3_IRQHandler, + EGU4_IRQHandler, + EGU5_IRQHandler, + PWM0_IRQHandler, + PWM1_IRQHandler, + PWM2_IRQHandler, + PWM3_IRQHandler, + 0, /* Reserved */ + PDM_IRQHandler, + 0, /* Reserved */ + I2S_IRQHandler, + 0, /* Reserved */ + IPC_IRQHandler, + 0, /* Reserved */ + FPU_IRQHandler, + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + GPIOTE1_IRQHandler, + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + KMU_IRQHandler, + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + CRYPTOCELL_IRQHandler, +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/target_cfg.h b/nrfdemo/build/tfm/api_ns/platform/common/core/target_cfg.h new file mode 100644 index 0000000..aea09be --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/target_cfg.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2017-2019 Arm Limited + * Copyright (c) 2020 Nordic Semiconductor ASA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __TARGET_CFG_H__ +#define __TARGET_CFG_H__ + +/** + * \file target_cfg.h + * \brief Target configuration header + * + * This file contains the platform specific functions to configure + * the Cortex-M33 core, memory permissions and security attribution. + * on the nordic_nrf platform. + * + * Memory permissions and security attribution are configured via + * the System Protection Unit (SPU) which is the nRF specific Implementation + * Defined Attribution Unit (IDAU). + */ + + +#include "tfm_plat_defs.h" +#include "region_defs.h" + +#if NRF_SECURE_UART_INSTANCE == 0 +#define TFM_DRIVER_STDIO Driver_USART0 +#elif NRF_SECURE_UART_INSTANCE == 1 +#define TFM_DRIVER_STDIO Driver_USART1 +#elif NRF_SECURE_UART_INSTANCE == 00 +#define TFM_DRIVER_STDIO Driver_USART00 +#elif NRF_SECURE_UART_INSTANCE == 20 +#define TFM_DRIVER_STDIO Driver_USART20 +#elif NRF_SECURE_UART_INSTANCE == 21 +#define TFM_DRIVER_STDIO Driver_USART21 +#elif NRF_SECURE_UART_INSTANCE == 22 +#define TFM_DRIVER_STDIO Driver_USART22 +#elif NRF_SECURE_UART_INSTANCE == 30 +#define TFM_DRIVER_STDIO Driver_USART30 +#endif + +/* Only UART20 and UART30 are supported for TF-M tests, which are the + * Non-secure applications build via the TF-M build system + */ +#ifdef NRF54L15_ENGA_XXAA +#if NRF_SECURE_UART_INSTANCE == 20 +#define NS_DRIVER_STDIO Driver_USART30 +#else +#define NS_DRIVER_STDIO Driver_USART20 +#endif +#else +#define NS_DRIVER_STDIO Driver_USART0 +#endif + +/** + * \brief Store the addresses of memory regions + */ +struct memory_region_limits { + uint32_t non_secure_code_start; + uint32_t non_secure_partition_base; + uint32_t non_secure_partition_limit; + uint32_t veneer_base; + uint32_t veneer_limit; +#ifdef NRF_NS_SECONDARY + uint32_t secondary_partition_base; + uint32_t secondary_partition_limit; +#endif /* NRF_NS_SECONDARY */ +#ifdef NRF_NS_STORAGE_PARTITION_START + uint32_t non_secure_storage_partition_base; + uint32_t non_secure_storage_partition_limit; +#endif /* NRF_NS_STORAGE_PARTITION_START */ +}; + +/** + * \brief Holds the data necessary to do isolation for a specific peripheral. + */ +struct platform_data_t +{ + uint32_t periph_start; + uint32_t periph_limit; +}; + +/** + * \brief Configures memory permissions via the System Protection Unit. + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t spu_init_cfg(void); + +/** + * \brief Configures peripheral permissions via the System Protection Unit. + * + * The function does the following: + * - grants Non-Secure access to nRF peripherals that are not Secure-only + * - grants Non-Secure access to DDPI channels + * - grants Non-Secure access to GPIO pins + * - On nrf5340 enforces that the external domain is still at the HW reset value + * of non-secure and locking it + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t spu_periph_init_cfg(void); + +/** + * \brief Configures memory permissions via the MPC. + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t nrf_mpc_init_cfg(void); + +/** + * \brief Configures SAU and IDAU. + */ +void sau_and_idau_cfg(void); + +/** + * \brief Enables the fault handlers and sets priorities. + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t enable_fault_handlers(void); + +/** + * \brief Configures the system reset request properties + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t system_reset_cfg(void); + +/** + * \brief Configures the system debug properties. + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t init_debug(void); + +/** + * \brief Configures all external interrupts to target the + * NS state, apart for the ones associated to secure + * peripherals (plus SPU) + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); + +/** + * \brief This function enable the interrupts associated + * to the secure peripherals (plus the isolation boundary violation + * interrupts) + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t nvic_interrupt_enable(void); + +#endif /* __TARGET_CFG_H__ */ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/core/tests/tfm_tests_config.cmake b/nrfdemo/build/tfm/api_ns/platform/common/core/tests/tfm_tests_config.cmake new file mode 100644 index 0000000..419b1d8 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/core/tests/tfm_tests_config.cmake @@ -0,0 +1,12 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +set(PLATFORM_SLIH_IRQ_TEST_SUPPORT ON) +set(PLATFORM_FLIH_IRQ_TEST_SUPPORT ON) + +# Make FLIH IRQ test as the default IRQ test on nordic platforms +set(TEST_NS_SLIH_IRQ OFF CACHE BOOL "Whether to build NS regression Second-Level Interrupt Handling tests") diff --git a/nrfdemo/build/tfm/api_ns/platform/common/crypto_keys.c b/nrfdemo/build/tfm/api_ns/platform/common/crypto_keys.c new file mode 100644 index 0000000..3e015a3 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/crypto_keys.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2021 - 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include <stddef.h> + +#include "psa/crypto_types.h" +#include "tfm_plat_crypto_keys.h" +#include "tfm_builtin_key_ids.h" +#include "tfm_builtin_key_loader.h" +#include "psa_manifest/pid.h" +#include "tfm_spm_log.h" + +#ifdef CONFIG_HW_UNIQUE_KEY +#include <hw_unique_key.h> +#endif + +#include <identity_key.h> + +#define TFM_NS_PARTITION_ID -1 + +#ifdef CONFIG_HW_UNIQUE_KEY +static enum tfm_plat_err_t tfm_plat_get_huk(uint8_t *buf, size_t buf_len, size_t *key_len, + size_t *key_bits, psa_algorithm_t *algorithm, + psa_key_type_t *type) +{ + if (buf_len < HUK_SIZE_BYTES) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + uint8_t label[] = "TFM_HW_UNIQ_KEY"; + + int err = hw_unique_key_derive_key(HUK_KEYSLOT_MEXT, NULL, 0, label, sizeof(label), buf, + buf_len); + + if (err != HW_UNIQUE_KEY_SUCCESS) { + SPMLOG_DBGMSGVAL("hw_unique_key_derive_key err: ", err); + + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + *key_len = HUK_SIZE_BYTES; + *key_bits = HUK_SIZE_BYTES * 8; + *algorithm = PSA_ALG_HKDF(PSA_ALG_SHA_256); + *type = PSA_KEY_TYPE_DERIVE; + + return TFM_PLAT_ERR_SUCCESS; +} +#endif /* CONFIG_HW_UNQUE_KEY */ + +#ifdef TFM_PARTITION_INITIAL_ATTESTATION +static enum tfm_plat_err_t tfm_plat_get_iak(uint8_t *buf, size_t buf_len, size_t *key_len, + size_t *key_bits, psa_algorithm_t *algorithm, + psa_key_type_t *type) +{ + int err; + + if (buf_len < IDENTITY_KEY_SIZE_BYTES) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + err = identity_key_read(buf); + if (err != IDENTITY_KEY_SUCCESS) { + SPMLOG_DBGMSGVAL("identity_key_read err: ", err); + + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + *key_len = IDENTITY_KEY_SIZE_BYTES; + *key_bits = IDENTITY_KEY_SIZE_BYTES * 8; + *algorithm = PSA_ALG_ECDSA(PSA_ALG_SHA_256); + *type = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); + + return TFM_PLAT_ERR_SUCCESS; +} + +/** + * @brief Table describing per-user key policy for the IAK + * + */ +static const tfm_plat_builtin_key_per_user_policy_t g_iak_per_user_policy[] = { + { + .user = TFM_SP_INITIAL_ATTESTATION, +#ifdef SYMMETRIC_INITIAL_ATTESTATION + .usage = PSA_KEY_USAGE_SIGN_HASH | PSA_KEY_USAGE_EXPORT, +#else + .usage = PSA_KEY_USAGE_SIGN_HASH, +#endif /* SYMMETRIC_INITIAL_ATTESTATION */ + }, +#ifdef TEST_S_ATTESTATION + {.user = TFM_SP_SECURE_TEST_PARTITION, .usage = PSA_KEY_USAGE_VERIFY_HASH}, +#endif /* TEST_S_ATTESTATION */ +#ifdef TEST_NS_ATTESTATION + {.user = TFM_NS_PARTITION_ID, .usage = PSA_KEY_USAGE_VERIFY_HASH}, +#endif /* TEST_NS_ATTESTATION */ +}; +#endif /* TFM_PARTITION_INITIAL_ATTESTATION */ + +/** + * @brief Table describing per-key user policies + * + */ +#if defined(CONFIG_HW_UNIQUE_KEY) || defined(TFM_PARTITION_INITIAL_ATTESTATION) +static const tfm_plat_builtin_key_policy_t g_builtin_keys_policy[] = { +#ifdef CONFIG_HW_UNIQUE_KEY + {.key_id = TFM_BUILTIN_KEY_ID_HUK, .per_user_policy = 0, .usage = PSA_KEY_USAGE_DERIVE}, +#endif /* CONFIG_HW_UNIQUE_KEY */ +#ifdef TFM_PARTITION_INITIAL_ATTESTATION + {.key_id = TFM_BUILTIN_KEY_ID_IAK, + .per_user_policy = ARRAY_SIZE(g_iak_per_user_policy), + .policy_ptr = g_iak_per_user_policy}, +#endif /* TFM_PARTITION_INITIAL_ATTESTATION */ +}; +#endif /* defined(CONFIG_HW_UNIQUE_KEY) || defined(TFM_PARTITION_INITIAL_ATTESTATION) */ + +/** + * @brief Table describing the builtin-in keys (plaform keys) available in the platform. Note + * that to bind the keys to the tfm_builtin_key_loader driver, the lifetime must be + * explicitly set to the one associated to the driver, i.e. TFM_BUILTIN_KEY_LOADER_LIFETIME + */ +#if defined(CONFIG_HW_UNIQUE_KEY) || defined(TFM_PARTITION_INITIAL_ATTESTATION) +static const tfm_plat_builtin_key_descriptor_t g_builtin_keys_desc[] = { +#ifdef CONFIG_HW_UNIQUE_KEY + {.key_id = TFM_BUILTIN_KEY_ID_HUK, + .slot_number = TFM_BUILTIN_KEY_SLOT_HUK, + .lifetime = TFM_BUILTIN_KEY_LOADER_LIFETIME, + .loader_key_func = tfm_plat_get_huk}, +#endif /* CONFIG_HW_UNIQUE_KEY */ +#ifdef TFM_PARTITION_INITIAL_ATTESTATION + {.key_id = TFM_BUILTIN_KEY_ID_IAK, + .slot_number = TFM_BUILTIN_KEY_SLOT_IAK, + .lifetime = TFM_BUILTIN_KEY_LOADER_LIFETIME, + .loader_key_func = tfm_plat_get_iak}, +#endif /* TFM_PARTITION_INITIAL_ATTESTATION */ + {}, +}; +#endif /* defined(CONFIG_HW_UNIQUE_KEY) || defined(TFM_PARTITION_INITIAL_ATTESTATION) */ + +size_t tfm_plat_builtin_key_get_policy_table_ptr(const tfm_plat_builtin_key_policy_t *desc_ptr[]) +{ +#if defined(CONFIG_HW_UNIQUE_KEY) || defined(TFM_PARTITION_INITIAL_ATTESTATION) + *desc_ptr = &g_builtin_keys_policy[0]; + return ARRAY_SIZE(g_builtin_keys_policy); +#else + return 0; +#endif +} + +size_t tfm_plat_builtin_key_get_desc_table_ptr(const tfm_plat_builtin_key_descriptor_t *desc_ptr[]) +{ +#if defined(CONFIG_HW_UNIQUE_KEY) || defined(TFM_PARTITION_INITIAL_ATTESTATION) + *desc_ptr = &g_builtin_keys_desc[0]; + return ARRAY_SIZE(g_builtin_keys_desc); +#else + return 0; +#endif /* defined(CONFIG_HW_UNIQUE_KEY) || defined(TFM_PARTITION_INITIAL_ATTESTATION) */ +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/dummy_otp.c b/nrfdemo/build/tfm/api_ns/platform/common/dummy_otp.c new file mode 100644 index 0000000..e255b52 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/dummy_otp.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2022 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include "tfm_plat_otp.h" + +enum tfm_plat_err_t tfm_plat_otp_init(void) +{ + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_read(enum tfm_otp_element_id_t id, size_t out_len, uint8_t *out) +{ + return TFM_PLAT_ERR_UNSUPPORTED; +} + +enum tfm_plat_err_t tfm_plat_otp_write(enum tfm_otp_element_id_t id, size_t in_len, + const uint8_t *in) +{ + return TFM_PLAT_ERR_UNSUPPORTED; +} + +enum tfm_plat_err_t tfm_plat_otp_get_size(enum tfm_otp_element_id_t id, size_t *size) +{ + return TFM_PLAT_ERR_UNSUPPORTED; +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/dummy_provisioning.c b/nrfdemo/build/tfm/api_ns/platform/common/dummy_provisioning.c new file mode 100644 index 0000000..56ebf6c --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/dummy_provisioning.c @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2022 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include "tfm_plat_provisioning.h" + +int tfm_plat_provisioning_is_required(void) +{ + return 0; +} + +enum tfm_plat_err_t tfm_plat_provisioning_perform(void) +{ + return TFM_PLAT_ERR_SUCCESS; +} + +void tfm_plat_provisioning_check_for_dummy_keys(void) +{ +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/dummy_tfm_sp_log_raw.c b/nrfdemo/build/tfm/api_ns/platform/common/dummy_tfm_sp_log_raw.c new file mode 100644 index 0000000..8eb75c9 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/dummy_tfm_sp_log_raw.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include <stdarg.h> +#include <stddef.h> + +/* This function is here in case any references to printf has been accidentally + * left in the code. This will then mute this printfs from pulling in the real + * printf instead of the function defined in tfm_sp_log_raw.c when this file + * is not part of the build. + */ +int printf(const char *fmt, ...) +{ + return 0; +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/dummy_uart_stdout.c b/nrfdemo/build/tfm/api_ns/platform/common/dummy_uart_stdout.c new file mode 100644 index 0000000..6faae12 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/dummy_uart_stdout.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2022 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include "uart_stdout.h" + +int stdio_output_string(const unsigned char *str, uint32_t len) +{ + return 0; +} + +void stdio_init(void) +{ +} + +void stdio_uninit(void) +{ +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/nrf91/CMakeLists.txt b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/CMakeLists.txt new file mode 100644 index 0000000..290d7f4 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/CMakeLists.txt @@ -0,0 +1,31 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. +# Copyright (c) 2020, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf91) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../core nrf_common) + +#========================= Platform Non-Secure ================================# + +target_include_directories(platform_ns + PUBLIC + . +) + +target_sources(platform_ns + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf91.c +) + +target_compile_definitions(platform_ns + PUBLIC + NRF_TRUSTZONE_NONSECURE + DOMAIN_NS=1 +) diff --git a/nrfdemo/build/tfm/api_ns/platform/common/nrf91/config.cmake b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/config.cmake new file mode 100644 index 0000000..39740bc --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/config.cmake @@ -0,0 +1,14 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2020-2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/core/config.cmake) + +set(SECURE_UART1 ON CACHE BOOL "Enable secure UART1") +set(NRF_NS_STORAGE OFF CACHE BOOL "Enable non-secure storage partition") +set(BL2 ON CACHE BOOL "Whether to build BL2") +set(NRF_NS_SECONDARY ${BL2} CACHE BOOL "Enable non-secure secondary partition") diff --git a/nrfdemo/build/tfm/api_ns/platform/common/nrf91/nrfx_config_nrf91.h b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/nrfx_config_nrf91.h new file mode 100644 index 0000000..e95f392 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/nrfx_config_nrf91.h @@ -0,0 +1,1657 @@ +/* + * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_CONFIG_NRF91_H__ +#define NRFX_CONFIG_NRF91_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + +/* + * The MDK for nRF9120 used in the nRF9161 target doesn't define the Secure FPU + * as it doesn't exist, but for other platforms like the 9160 it has a dummy + * define. + * Therefore we define it here manually until it is fixed in the MDK. + * See: NCSDK-23046 + */ +#ifdef NRF9120_XXAA +#define NRF_FPU_S 1 +#endif + +#define NRF_CLOCK NRF_PERIPH(NRF_CLOCK) +#define NRF_DPPIC NRF_PERIPH(NRF_DPPIC) +#define NRF_EGU0 NRF_PERIPH(NRF_EGU0) +#define NRF_EGU1 NRF_PERIPH(NRF_EGU1) +#define NRF_EGU2 NRF_PERIPH(NRF_EGU2) +#define NRF_EGU3 NRF_PERIPH(NRF_EGU3) +#define NRF_EGU4 NRF_PERIPH(NRF_EGU4) +#define NRF_EGU5 NRF_PERIPH(NRF_EGU5) +#define NRF_FPU NRF_PERIPH(NRF_FPU) +#define NRF_IPC NRF_PERIPH(NRF_IPC) +#define NRF_I2S NRF_PERIPH(NRF_I2S) +#define NRF_KMU NRF_PERIPH(NRF_KMU) +#define NRF_NVMC NRF_PERIPH(NRF_NVMC) +#define NRF_P0 NRF_PERIPH(NRF_P0) +#define NRF_PDM NRF_PERIPH(NRF_PDM) +#define NRF_POWER NRF_PERIPH(NRF_POWER) +#define NRF_PWM0 NRF_PERIPH(NRF_PWM0) +#define NRF_PWM1 NRF_PERIPH(NRF_PWM1) +#define NRF_PWM2 NRF_PERIPH(NRF_PWM2) +#define NRF_PWM3 NRF_PERIPH(NRF_PWM3) +#define NRF_REGULATORS NRF_PERIPH(NRF_REGULATORS) +#define NRF_RTC0 NRF_PERIPH(NRF_RTC0) +#define NRF_RTC1 NRF_PERIPH(NRF_RTC1) +#define NRF_SAADC NRF_PERIPH(NRF_SAADC) +#define NRF_SPIM0 NRF_PERIPH(NRF_SPIM0) +#define NRF_SPIM1 NRF_PERIPH(NRF_SPIM1) +#define NRF_SPIM2 NRF_PERIPH(NRF_SPIM2) +#define NRF_SPIM3 NRF_PERIPH(NRF_SPIM3) +#define NRF_SPIS0 NRF_PERIPH(NRF_SPIS0) +#define NRF_SPIS1 NRF_PERIPH(NRF_SPIS1) +#define NRF_SPIS2 NRF_PERIPH(NRF_SPIS2) +#define NRF_SPIS3 NRF_PERIPH(NRF_SPIS3) +#define NRF_TIMER0 NRF_PERIPH(NRF_TIMER0) +#define NRF_TIMER1 NRF_PERIPH(NRF_TIMER1) +#define NRF_TIMER2 NRF_PERIPH(NRF_TIMER2) +#define NRF_TWIM0 NRF_PERIPH(NRF_TWIM0) +#define NRF_TWIM1 NRF_PERIPH(NRF_TWIM1) +#define NRF_TWIM2 NRF_PERIPH(NRF_TWIM2) +#define NRF_TWIM3 NRF_PERIPH(NRF_TWIM3) +#define NRF_TWIS0 NRF_PERIPH(NRF_TWIS0) +#define NRF_TWIS1 NRF_PERIPH(NRF_TWIS1) +#define NRF_TWIS2 NRF_PERIPH(NRF_TWIS2) +#define NRF_TWIS3 NRF_PERIPH(NRF_TWIS3) +#define NRF_UARTE0 NRF_PERIPH(NRF_UARTE0) +#define NRF_UARTE1 NRF_PERIPH(NRF_UARTE1) +#define NRF_UARTE2 NRF_PERIPH(NRF_UARTE2) +#define NRF_UARTE3 NRF_PERIPH(NRF_UARTE3) +#define NRF_VMC NRF_PERIPH(NRF_VMC) +#define NRF_WDT NRF_PERIPH(NRF_WDT) + +/* + * The following section provides the name translation for peripherals with + * only one type of access available. For these peripherals, you cannot choose + * between secure and non-secure mapping. + */ +#if defined(NRF_TRUSTZONE_NONSECURE) +#define NRF_GPIOTE1 NRF_GPIOTE1_NS +#else +#define NRF_CC_HOST_RGF NRF_CC_HOST_RGF_S +#define NRF_CRYPTOCELL NRF_CRYPTOCELL_S +#define NRF_CTRL_AP_PERI NRF_CTRL_AP_PERI_S +#define NRF_FICR NRF_FICR_S +#define NRF_GPIOTE0 NRF_GPIOTE0_S +#define NRF_SPU NRF_SPU_S +#define NRF_TAD NRF_TAD_S +#define NRF_UICR NRF_UICR_S +#endif + +/* Fixup for the GPIOTE driver. */ +#if defined(NRF_TRUSTZONE_NONSECURE) +#define NRF_GPIOTE NRF_GPIOTE1 +#else +#define NRF_GPIOTE NRF_GPIOTE0 +#endif + + +// <<< Use Configuration Wizard in Context Menu >>>\n + +// <h> nRF_Drivers + +// <e> NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver. +//========================================================== +#ifndef NRFX_CLOCK_ENABLED +#define NRFX_CLOCK_ENABLED 0 +#endif +// <o> NRFX_CLOCK_CONFIG_LF_SRC - LF clock source. + +// <1=> RC +// <2=> XTAL + +#ifndef NRFX_CLOCK_CONFIG_LF_SRC +#define NRFX_CLOCK_CONFIG_LF_SRC 2 +#endif + +// <q> NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// <i> If set to a non-zero value, LFRC will be started before LFXO and corresponding +// <i> event will be generated. It means that CPU will be woken up when LFRC +// <i> oscillator starts, but user callback will be invoked only after LFXO +// <i> finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + + +// <o> NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED +#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_CLOCK_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL +#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR +#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR +#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_DPPI_ENABLED - nrfx_dppi - DPPI allocator. +//========================================================== +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif +// <e> NRFX_DPPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED +#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_DPPI_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL +#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_DPPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_DPPI_CONFIG_INFO_COLOR +#define NRFX_DPPI_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_DPPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_DPPI_CONFIG_DEBUG_COLOR +#define NRFX_DPPI_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_EGU_ENABLED - nrfx_egu - EGU peripheral driver. +//========================================================== +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +// <q> NRFX_EGU0_ENABLED - Enable EGU0 instance. + +#ifndef NRFX_EGU0_ENABLED +#define NRFX_EGU0_ENABLED 0 +#endif + +// <q> NRFX_EGU1_ENABLED - Enable EGU1 instance. + +#ifndef NRFX_EGU1_ENABLED +#define NRFX_EGU1_ENABLED 0 +#endif + +// <q> NRFX_EGU2_ENABLED - Enable EGU2 instance. + +#ifndef NRFX_EGU2_ENABLED +#define NRFX_EGU2_ENABLED 0 +#endif + +// <q> NRFX_EGU3_ENABLED - Enable EGU3 instance. + +#ifndef NRFX_EGU3_ENABLED +#define NRFX_EGU3_ENABLED 0 +#endif + +// <q> NRFX_EGU4_ENABLED - Enable EGU4 instance. + +#ifndef NRFX_EGU4_ENABLED +#define NRFX_EGU4_ENABLED 0 +#endif + +// <q> NRFX_EGU5_ENABLED - Enable EGU5 instance. + +#ifndef NRFX_EGU5_ENABLED +#define NRFX_EGU5_ENABLED 0 +#endif + +// <o> NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// </e> + +// <e> NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver. +//========================================================== +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 0 +#endif +// <o> NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins. +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 +#endif + +// <o> NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR +#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR +#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver. +//========================================================== +#ifndef NRFX_I2S_ENABLED +#define NRFX_I2S_ENABLED 0 +#endif + +// <o> NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_I2S_CONFIG_LOG_ENABLED +#define NRFX_I2S_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_I2S_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_I2S_CONFIG_LOG_LEVEL +#define NRFX_I2S_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_I2S_CONFIG_INFO_COLOR +#define NRFX_I2S_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR +#define NRFX_I2S_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_IPC_ENABLED - nrfx_ipc - IPC peripheral driver +//========================================================== +#ifndef NRFX_IPC_ENABLED +#define NRFX_IPC_ENABLED 0 +#endif + +// </e> + +// <e> NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver +//========================================================== +#ifndef NRFX_NVMC_ENABLED +#define NRFX_NVMC_ENABLED 0 +#endif + +// </e> + +// <e> NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver. +//========================================================== +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif + +// <o> NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_PDM_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PDM_CONFIG_INFO_COLOR +#define NRFX_PDM_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR +#define NRFX_PDM_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver. +//========================================================== +#ifndef NRFX_POWER_ENABLED +#define NRFX_POWER_ENABLED 0 +#endif +// <o> NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// </e> + +// <e> NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing (PRS) module. +//========================================================== +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 0 +#endif +// <q> NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module. + + +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 0 +#endif + +// <q> NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module. + + +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 0 +#endif + +// <q> NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module. + + +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 0 +#endif + +// <q> NRFX_PRS_BOX_3_ENABLED - Enables box 3 in the module. + + +#ifndef NRFX_PRS_BOX_3_ENABLED +#define NRFX_PRS_BOX_3_ENABLED 0 +#endif + +// <e> NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_PRS_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PRS_CONFIG_INFO_COLOR +#define NRFX_PRS_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR +#define NRFX_PRS_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver. +//========================================================== +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif +// <q> NRFX_PWM0_ENABLED - Enables PWM0 instance. + + +#ifndef NRFX_PWM0_ENABLED +#define NRFX_PWM0_ENABLED 0 +#endif + +// <q> NRFX_PWM1_ENABLED - Enables PWM1 instance. + + +#ifndef NRFX_PWM1_ENABLED +#define NRFX_PWM1_ENABLED 0 +#endif + +// <q> NRFX_PWM2_ENABLED - Enables PWM2 instance. + + +#ifndef NRFX_PWM2_ENABLED +#define NRFX_PWM2_ENABLED 0 +#endif + +// <q> NRFX_PWM3_ENABLED - Enables PWM3 instance. + + +#ifndef NRFX_PWM3_ENABLED +#define NRFX_PWM3_ENABLED 0 +#endif + +// <o> NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_PWM_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PWM_CONFIG_INFO_COLOR +#define NRFX_PWM_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR +#define NRFX_PWM_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver. +//========================================================== +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif +// <q> NRFX_RTC0_ENABLED - Enables RTC0 instance. + + +#ifndef NRFX_RTC0_ENABLED +#define NRFX_RTC0_ENABLED 0 +#endif + +// <q> NRFX_RTC1_ENABLED - Enables RTC1 instance. + + +#ifndef NRFX_RTC1_ENABLED +#define NRFX_RTC1_ENABLED 0 +#endif + +// <o> NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_RTC_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_INFO_COLOR +#define NRFX_RTC_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR +#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver. +//========================================================== +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif + +// <o> NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_SAADC_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_INFO_COLOR +#define NRFX_SAADC_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR +#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver. +//========================================================== +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif +// <q> NRFX_SPIM0_ENABLED - Enables SPIM0 instance. + + +#ifndef NRFX_SPIM0_ENABLED +#define NRFX_SPIM0_ENABLED 0 +#endif + +// <q> NRFX_SPIM1_ENABLED - Enables SPIM1 instance. + + +#ifndef NRFX_SPIM1_ENABLED +#define NRFX_SPIM1_ENABLED 0 +#endif + +// <q> NRFX_SPIM2_ENABLED - Enables SPIM2 instance. + + +#ifndef NRFX_SPIM2_ENABLED +#define NRFX_SPIM2_ENABLED 0 +#endif + +// <q> NRFX_SPIM3_ENABLED - Enables SPIM3 instance. + + +#ifndef NRFX_SPIM3_ENABLED +#define NRFX_SPIM3_ENABLED 0 +#endif + +// <o> NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_SPIM_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_INFO_COLOR +#define NRFX_SPIM_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR +#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver. +//========================================================== +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif +// <q> NRFX_SPIS0_ENABLED - Enables SPIS0 instance. + + +#ifndef NRFX_SPIS0_ENABLED +#define NRFX_SPIS0_ENABLED 0 +#endif + +// <q> NRFX_SPIS1_ENABLED - Enables SPIS1 instance. + + +#ifndef NRFX_SPIS1_ENABLED +#define NRFX_SPIS1_ENABLED 0 +#endif + +// <q> NRFX_SPIS2_ENABLED - Enables SPIS2 instance. + + +#ifndef NRFX_SPIS2_ENABLED +#define NRFX_SPIS2_ENABLED 0 +#endif + +// <q> NRFX_SPIS3_ENABLED - Enables SPIS3 instance. + + +#ifndef NRFX_SPIS3_ENABLED +#define NRFX_SPIS3_ENABLED 0 +#endif + +// <o> NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_SPIS_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_INFO_COLOR +#define NRFX_SPIS_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR +#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <q> NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver. + + +#ifndef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED 0 +#endif + +// <e> NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver. +//========================================================== +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif + +// <q> NRFX_TIMER0_ENABLED - Enables TIMER0 instance. + +#ifndef NRFX_TIMER0_ENABLED +#define NRFX_TIMER0_ENABLED 0 +#endif + +// <q> NRFX_TIMER1_ENABLED - Enables TIMER1 instance. + +#ifndef NRFX_TIMER1_ENABLED +#define NRFX_TIMER1_ENABLED 0 +#endif + +// <q> NRFX_TIMER2_ENABLED - Enables TIMER2 instance. + +#ifndef NRFX_TIMER2_ENABLED +#define NRFX_TIMER2_ENABLED 0 +#endif + +// <o> NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_TIMER_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_INFO_COLOR +#define NRFX_TIMER_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR +#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver. +//========================================================== +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif +// <q> NRFX_TWIM0_ENABLED - Enables TWIM0 instance. + + +#ifndef NRFX_TWIM0_ENABLED +#define NRFX_TWIM0_ENABLED 0 +#endif + +// <q> NRFX_TWIM1_ENABLED - Enables TWIM1 instance. + + +#ifndef NRFX_TWIM1_ENABLED +#define NRFX_TWIM1_ENABLED 0 +#endif + +// <q> NRFX_TWIM2_ENABLED - Enables TWIM2 instance. + + +#ifndef NRFX_TWIM2_ENABLED +#define NRFX_TWIM2_ENABLED 0 +#endif + +// <q> NRFX_TWIM3_ENABLED - Enables TWIM3 instance. + + +#ifndef NRFX_TWIM3_ENABLED +#define NRFX_TWIM3_ENABLED 0 +#endif + +// <o> NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_TWIM_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_INFO_COLOR +#define NRFX_TWIM_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR +#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver. +//========================================================== +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif +// <q> NRFX_TWIS0_ENABLED - Enables TWIS0 instance. + + +#ifndef NRFX_TWIS0_ENABLED +#define NRFX_TWIS0_ENABLED 0 +#endif + +// <q> NRFX_TWIS1_ENABLED - Enables TWIS1 instance. + + +#ifndef NRFX_TWIS1_ENABLED +#define NRFX_TWIS1_ENABLED 0 +#endif + +// <q> NRFX_TWIS2_ENABLED - Enables TWIS2 instance. + + +#ifndef NRFX_TWIS2_ENABLED +#define NRFX_TWIS2_ENABLED 0 +#endif + +// <q> NRFX_TWIS3_ENABLED - Enables TWIS3 instance. + + +#ifndef NRFX_TWIS3_ENABLED +#define NRFX_TWIS3_ENABLED 0 +#endif + +// <q> NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assumes that any instance would be initialized only once. + + +// <i> Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// <q> NRFX_TWIS_NO_SYNC_MODE - Removes support for synchronous mode. + +// <i> Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +// <o> NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_TWIS_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_INFO_COLOR +#define NRFX_TWIS_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR +#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver. +//========================================================== +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif +// <q> NRFX_UARTE0_ENABLED - Enables UARTE0 instances +#ifndef NRFX_UARTE0_ENABLED +#define NRFX_UARTE0_ENABLED 0 +#endif + +// <q> NRFX_UARTE1_ENABLED - Enables UARTE1 instance. +#ifndef NRFX_UARTE1_ENABLED +#define NRFX_UARTE1_ENABLED 0 +#endif + +// <q> NRFX_UARTE2_ENABLED - Enables UARTE2 instance. +#ifndef NRFX_UARTE2_ENABLED +#define NRFX_UARTE2_ENABLED 0 +#endif + +// <q> NRFX_UARTE3_ENABLED - Enables UARTE3 instance. +#ifndef NRFX_UARTE3_ENABLED +#define NRFX_UARTE3_ENABLED 0 +#endif + +// <o> NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_UARTE_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_INFO_COLOR +#define NRFX_UARTE_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR +#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// <e> NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver. +//========================================================== +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif +// <q> NRFX_WDT0_ENABLED - Enable WDT0 instance. + + +#ifndef NRFX_WDT0_ENABLED +#define NRFX_WDT0_ENABLED 0 +#endif + +// <o> NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver. + +// <0=> Include WDT IRQ handling +// <1=> Remove WDT IRQ handling + +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +// <o> NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// <e> NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif +// <o> NRFX_WDT_CONFIG_LOG_LEVEL - Default severity level. + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +// <o> NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_INFO_COLOR +#define NRFX_WDT_CONFIG_INFO_COLOR 0 +#endif + +// <o> NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR +#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 +#endif + +// </e> + +// </e> + +// </h> + +#endif // NRFX_CONFIG_NRF91_H__ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/flash_layout.h b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/flash_layout.h new file mode 100644 index 0000000..ca15bda --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/flash_layout.h @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +/* Flash layout on nRF91 with BL2: + * + * 0x0000_0000 BL2 - MCUBoot (64 KB) + * 0x0001_0000 Primary image area (448 KB): + * 0x0001_0000 Secure image primary (256 KB) + * 0x0005_0000 Non-secure image primary (192 KB) + * 0x0008_0000 Secondary image area (448 KB): + * 0x0008_0000 Secure image secondary (256 KB) + * 0x000c_0000 Non-secure image secondary (192 KB) + * 0x000f_0000 Protected Storage Area (16 KB) + * 0x000f_4000 Internal Trusted Storage Area (8 KB) + * 0x000f_6000 OTP / NV counters area (8 KB) + * 0x000f_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + * + * Flash layout on nRF91 without BL2: + * + * 0x0000_0000 Primary image area (960 KB): + * 0x0000_0000 Secure image primary (480 KB) + * 0x0007_8000 Non-secure image primary (480 KB) + * 0x000f_0000 Protected Storage Area (16 KB) + * 0x000f_4000 Internal Trusted Storage Area (8 KB) + * 0x000f_6000 OTP / NV counters area (8 KB) + * 0x000f_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_base_address.h to access flash related defines. To resolve + * this some of the values are redefined here with different names, these are + * marked with comment. + */ + +/* Size of a Secure and of a Non-secure image */ +#ifdef PSA_API_TEST_IPC +/* Firmware Framework test suites */ +#define FLASH_S_PARTITION_SIZE (0x48000) /* S partition: 288 kB*/ +#define FLASH_NS_PARTITION_SIZE (0x28000) /* NS partition: 160 kB*/ +#else +#define FLASH_S_PARTITION_SIZE (0x40000) /* S partition: 256 kB*/ +#define FLASH_NS_PARTITION_SIZE (0x30000) /* NS partition: 192 kB*/ +#endif + +#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) +#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE +#else +#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE +#endif +/* Sector size of the embedded flash hardware (erase/program) */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB. Flash memory program/erase operations have a page granularity. */ + +/* FLASH size */ +#define FLASH_TOTAL_SIZE (0x100000) /* 1024 kB. */ + +/* Flash layout info for BL2 bootloader */ +#define FLASH_BASE_ADDRESS (0x00000000) + + +/* Offset and size definitions of the flash partitions that are handled by the + * bootloader. The image swapping is done between IMAGE_PRIMARY and + * IMAGE_SECONDARY, SCRATCH is used as a temporary storage during image + * swapping. + */ +#define FLASH_AREA_BL2_OFFSET (0x0) +#define FLASH_AREA_BL2_SIZE (0x10000) /* 64 KB */ + +#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1) +/* Secure + Non-secure image primary slot */ +#define FLASH_AREA_0_ID (1) +#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE) +#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) +/* Secure + Non-secure secondary slot */ +#define FLASH_AREA_2_ID (FLASH_AREA_0_ID + 1) +#define FLASH_AREA_2_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) +#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) +/* Not used, only the Non-swapping firmware upgrade operation + * is supported on nRF91. + */ +#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1) +#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) +#define FLASH_AREA_SCRATCH_SIZE (0) +/* Maximum number of image sectors supported by the bootloader. */ +#define MCUBOOT_MAX_IMG_SECTORS ((FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) / \ + FLASH_AREA_IMAGE_SECTOR_SIZE) +#elif (MCUBOOT_IMAGE_NUMBER == 2) +/* Secure image primary slot */ +#define FLASH_AREA_0_ID (1) +#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE) +#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE) +/* Non-secure image primary slot */ +#define FLASH_AREA_1_ID (FLASH_AREA_0_ID + 1) +#define FLASH_AREA_1_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) +#define FLASH_AREA_1_SIZE (FLASH_NS_PARTITION_SIZE) +/* Secure image secondary slot */ +#define FLASH_AREA_2_ID (FLASH_AREA_1_ID + 1) +#define FLASH_AREA_2_OFFSET (FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE) +#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE) +/* Non-secure image secondary slot */ +#define FLASH_AREA_3_ID (FLASH_AREA_2_ID + 1) +#define FLASH_AREA_3_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) +#define FLASH_AREA_3_SIZE (FLASH_NS_PARTITION_SIZE) +/* Not used, only the Non-swapping firmware upgrade operation + * is supported on nRF91. + */ +#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1) +#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE) +#define FLASH_AREA_SCRATCH_SIZE (0) +/* Maximum number of image sectors supported by the bootloader. */ +#define MCUBOOT_MAX_IMG_SECTORS (FLASH_MAX_PARTITION_SIZE / \ + FLASH_AREA_IMAGE_SECTOR_SIZE) +#else /* MCUBOOT_IMAGE_NUMBER > 2 */ +#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!" +#endif /* MCUBOOT_IMAGE_NUMBER */ + +/* Not used, only the Non-swapping firmware upgrade operation + * is supported on nRF91. The maximum number of status entries + * supported by the bootloader. + */ +#define MCUBOOT_STATUS_MAX_ENTRIES (0) + + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (FLASH_AREA_SCRATCH_OFFSET + \ + FLASH_AREA_SCRATCH_SIZE) +#define FLASH_PS_AREA_SIZE (0x4000) /* 16 KB */ + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + \ + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE (0x2000) /* 8 KB */ + +/* OTP_definitions */ +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + \ + FLASH_ITS_AREA_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE * 2) +#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + +/* Non-secure storage region */ +#define NRF_FLASH_NS_STORAGE_AREA_OFFSET (FLASH_TOTAL_SIZE - \ + NRF_FLASH_NS_STORAGE_AREA_SIZE) +#define NRF_FLASH_NS_STORAGE_AREA_SIZE (0x8000) /* 32 KB */ + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_OFFSET (0x0) +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE + +#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + \ + SECURE_IMAGE_MAX_SIZE) +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +/* Flash device name used by BL2 + * Name is defined in flash driver file: Driver_Flash.c + */ +#define FLASH_DEV_NAME Driver_FLASH0 +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x4) + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Size of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x4) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Size of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x4) + +/* OTP / NV counter definitions */ +#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) +#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET +#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE +#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \ + TFM_OTP_NV_COUNTERS_AREA_SIZE) + +/* Use Flash memory to store Code data */ +#define FLASH_BASE_ADDRESS (0x00000000) +#define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS +#define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS + +/* Use SRAM memory to store RW data */ +#define SRAM_BASE_ADDRESS (0x20000000) +#define S_RAM_ALIAS_BASE SRAM_BASE_ADDRESS +#define NS_RAM_ALIAS_BASE SRAM_BASE_ADDRESS + +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE +#define TOTAL_RAM_SIZE (0x00040000) /* 256 kB */ + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/region_defs.h b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/region_defs.h new file mode 100644 index 0000000..4a4ad59 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/region_defs.h @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#define BL2_HEAP_SIZE (0x00001000) +#define BL2_MSP_STACK_SIZE (0x00001800) + +#ifdef ENABLE_HEAP + #define S_HEAP_SIZE (0x0000200) +#endif + +#define S_MSP_STACK_SIZE (0x00000800) +#define S_PSP_STACK_SIZE (0x00000800) + +#define NS_HEAP_SIZE (0x00001000) +#define NS_STACK_SIZE (0x000001E0) + +/* Size of nRF SPU (Nordic IDAU) regions */ +#define SPU_FLASH_REGION_SIZE (0x00008000) +#define SPU_SRAM_REGION_SIZE (0x00002000) + +/* + * SPU flash region granularity is 32 KB on nRF91. Alignment + * of partitions is defined in accordance with this constraint. + */ +#ifdef NRF_NS_SECONDARY +#ifndef LINK_TO_SECONDARY_PARTITION +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#endif /* !LINK_TO_SECONDARY_PARTITION */ +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0) +#endif /* NRF_NS_SECONDARY */ + +#ifndef LINK_TO_SECONDARY_PARTITION +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \ + + FLASH_S_PARTITION_SIZE) +#else +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET \ + + FLASH_S_PARTITION_SIZE) +#endif /* !LINK_TO_SECONDARY_PARTITION */ + +/* Boot partition structure if MCUBoot is used: + * 0x0_0000 Bootloader header + * 0x0_0400 Image area + * 0x0_FC00 Trailer + */ +/* IMAGE_CODE_SIZE is the space available for the software binary image. + * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE + * because we reserve space for the image header and trailer introduced + * by the bootloader. + */ + +#if (!defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)) && \ + (NS_IMAGE_PRIMARY_PARTITION_OFFSET > S_IMAGE_PRIMARY_PARTITION_OFFSET) +/* If secure image and nonsecure image are concatenated, and nonsecure image + * locates at the higher memory range, then the secure image does not need + * the trailer area. + */ +#define IMAGE_S_CODE_SIZE \ + (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE) +#else +#define IMAGE_S_CODE_SIZE \ + (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) +#endif + +#define IMAGE_NS_CODE_SIZE \ + (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_IMAGE_PRIMARY_AREA_OFFSET \ + (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) +#define S_CODE_SIZE (IMAGE_S_CODE_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_START (S_RAM_ALIAS(0x0)) +/* Assign to SPE the minimum amount of RAM (aligned to the SPU region boundary) + * that is needed for the most demanding configuration, which turns out to be + * the RegressionIPC one. */ +#define S_DATA_SIZE 0x16000 /* 88 KB */ +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +#define S_CODE_VECTOR_TABLE_SIZE (0x144) + +#if defined(NULL_POINTER_EXCEPTION_DETECTION) && S_CODE_START == 0 +/* If this image is placed at the beginning of flash make sure we + * don't put any code in the first 256 bytes of flash as that area + * is used for null-pointer dereference detection. + */ +#define TFM_LINKER_CODE_START_RESERVED (256) +#if S_CODE_VECTOR_TABLE_SIZE < TFM_LINKER_CODE_START_RESERVED +#error "The interrupt table is too short too for null pointer detection" +#endif +#endif + +/* The veneers needs to be placed at the end of the secure image. + * This is because the NCS sub-region is defined as starting at the highest + * address of an SPU region and going downwards. + */ +#define TFM_LINKER_VENEERS_LOCATION_END +/* The CMSE veneers shall be placed in an NSC region + * which will be placed in a secure SPU region with the given alignment. + */ +#define TFM_LINKER_VENEERS_SIZE (0x400) +/* The Nordic SPU has different alignment requirements than the ARM SAU, so + * these override the default start and end alignments. */ +#define TFM_LINKER_VENEERS_START \ + (ALIGN(SPU_FLASH_REGION_SIZE) - TFM_LINKER_VENEERS_SIZE + \ + (. > (ALIGN(SPU_FLASH_REGION_SIZE) - TFM_LINKER_VENEERS_SIZE) \ + ? SPU_FLASH_REGION_SIZE : 0)) + +#define TFM_LINKER_VENEERS_END ALIGN(SPU_FLASH_REGION_SIZE) + +/* Non-secure regions */ +#define NS_IMAGE_PRIMARY_AREA_OFFSET \ + (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) +#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) +#ifdef PSA_API_TEST_IPC +/* Last SRAM region must be kept secure for PSA FF tests */ +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - SPU_SRAM_REGION_SIZE) +#else +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#endif +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for SPU configuration */ +#define NS_PARTITION_START \ + (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)) +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Secondary partition for new images in case of firmware upgrade */ +#define SECONDARY_PARTITION_START \ + (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET)) +#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) + +/* Non-secure storage region */ +#ifdef NRF_NS_STORAGE +#define NRF_NS_STORAGE_PARTITION_START \ + (NS_ROM_ALIAS(NRF_FLASH_NS_STORAGE_AREA_OFFSET)) +#define NRF_NS_STORAGE_PARTITION_SIZE (NRF_FLASH_NS_STORAGE_AREA_SIZE) +#endif /* NRF_NS_STORAGE */ + +#ifdef BL2 +/* Bootloader regions */ +#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET)) +#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE) +#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) + +#define BL2_DATA_START (S_RAM_ALIAS(0x0)) +#define BL2_DATA_SIZE (TOTAL_RAM_SIZE) +#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) +#endif /* BL2 */ + +/* Shared data area between bootloader and runtime firmware. + * Shared data area is allocated at the beginning of the RAM, it is overlapping + * with TF-M Secure code's MSP stack + */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE +#define BOOT_TFM_SHARED_DATA_SIZE (0x400) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ + BOOT_TFM_SHARED_DATA_SIZE - 1) + +/* Regions used by psa-arch-tests to keep state */ +#define PSA_TEST_SCRATCH_AREA_SIZE (0x400) + +#ifdef PSA_API_TEST_IPC +/* Firmware Framework test suites */ +#define FF_TEST_PARTITION_SIZE 0x100 +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE - \ + FF_TEST_PARTITION_SIZE) + +/* The psa-arch-tests implementation requires that the test partitions are + * placed in this specific order: + * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER + * + * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER + * must be in SPE. + * + * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation, + * and it should be placed at the end of the NSPE area, after + * PSA_TEST_SCRATCH_AREA. + */ +#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1) +#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#else +/* Development APIs test suites */ +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE) +#endif /* PSA_API_TEST_IPC */ + +#endif /* __REGION_DEFS_H__ */ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/nrf91/tests/psa_arch_tests_config.cmake b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000..5320c4c --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/tests/psa_arch_tests_config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# Platform-specific configurations +# Use nrf9160 until test target name in PSA arch test repository has been updated to nrf91 +set(PSA_API_TEST_TARGET "nrf9160") diff --git a/nrfdemo/build/tfm/api_ns/platform/common/nrf9120/cpuarch.cmake b/nrfdemo/build/tfm/api_ns/platform/common/nrf9120/cpuarch.cmake new file mode 100644 index 0000000..9af11fc --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/nrf9120/cpuarch.cmake @@ -0,0 +1,20 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# preload.cmake is used to set things that related to the platform that are both +# immutable and global, which is to say they should apply to any kind of project +# that uses this platform. In practise this is normally compiler definitions and +# variables related to hardware. + +# Set architecture and CPU +set(TFM_SYSTEM_PROCESSOR cortex-m33) +set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) +set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") + +add_compile_definitions( + NRF9120_XXAA + NRF91_SERIES +) diff --git a/nrfdemo/build/tfm/api_ns/platform/common/nrf_provisioning.c b/nrfdemo/build/tfm/api_ns/platform/common/nrf_provisioning.c new file mode 100644 index 0000000..4ce7792 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/nrf_provisioning.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2022 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include "tfm_plat_provisioning.h" +#include "tfm_plat_otp.h" +#include "tfm_platform_system.h" +#include "tfm_attest_hal.h" +#include "hw_unique_key.h" +#include "nrfx_nvmc.h" +#include <nrfx.h> +#include <nrf_cc3xx_platform.h> +#include <nrf_cc3xx_platform_identity_key.h> +#include "nrf_provisioning.h" +#include <identity_key.h> +#include <tfm_spm_log.h> + +static enum tfm_plat_err_t disable_debugging(void) +{ + /* Configure the UICR such that upon the next reset, APPROTECT will be enabled */ + bool approt_writable; + + approt_writable = nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->APPROTECT, + UICR_APPROTECT_PALL_Protected); + approt_writable &= nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, + UICR_SECUREAPPROTECT_PALL_Protected); + + if (approt_writable) { + nrfx_nvmc_word_write((uint32_t)&NRF_UICR_S->APPROTECT, + UICR_APPROTECT_PALL_Protected); + nrfx_nvmc_word_write((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, + UICR_SECUREAPPROTECT_PALL_Protected); + } else { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + return TFM_PLAT_ERR_SUCCESS; +} + +int tfm_plat_provisioning_is_required(void) +{ + enum tfm_security_lifecycle_t lcs; + + lcs = tfm_attest_hal_get_security_lifecycle(); + + return lcs == TFM_SLC_PSA_ROT_PROVISIONING; +} + +enum tfm_plat_err_t tfm_plat_provisioning_perform(void) +{ + enum tfm_security_lifecycle_t lcs; + + lcs = tfm_attest_hal_get_security_lifecycle(); + + /* + * Provisioning in NRF defines has two steps, the first step is to execute + * the provisioning_image sample. When this sample is executed it will + * always set the lifecycle state to PROVISIONING. This is a requirement for + * the TF-M provisioning to be completed so we don't accept any other + * lifecycle state here. + */ + + /* The Hardware Unique Keys should be already written */ + if (!hw_unique_key_are_any_written()) { + SPMLOG_ERRMSG("This device has not been provisioned with Hardware Unique Keys."); + return TFM_PLAT_ERR_SYSTEM_ERR; + } + +#ifdef TFM_PARTITION_INITIAL_ATTESTATION + /* The Initial Attestation key should be already written */ + if (!identity_key_is_written()) { + SPMLOG_ERRMSG( + "This device has not been provisioned with an Initial Attestation Key."); + return TFM_PLAT_ERR_SYSTEM_ERR; + } +#endif + + /* + * We don't need to make sure that the validation key is written here since we assume + * that secure boot is already enabled at this stage + */ + + /* Disable debugging in UICR */ + if (disable_debugging() != TFM_PLAT_ERR_SUCCESS) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* Transition to the SECURED lifecycle state */ + if (tfm_attest_update_security_lifecycle_otp(TFM_SLC_SECURED) != 0) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + lcs = tfm_attest_hal_get_security_lifecycle(); + if (lcs != TFM_SLC_SECURED) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* Perform a mandatory reset since we switch to an attestable LCS state */ + tfm_platform_hal_system_reset(); + + /* + * We should never return from this function, a reset should be triggered + * before we reach this point. Returning an error to signal that something + * is wrong if we reached here. + */ + return TFM_PLAT_ERR_SYSTEM_ERR; +} + +static bool dummy_key_is_present(void) +{ +#ifdef TFM_PARTITION_INITIAL_ATTESTATION + uint8_t key[IDENTITY_KEY_SIZE_BYTES]; + int err; + + err = identity_key_read(key); + if (err < 0) { + /* Unable to read out the key. Then it is likely not present. */ + return false; + } + + /* The first 8 bytes of the dummy key */ + uint8_t first_8_bytes[8] = {0xA9, 0xB4, 0x54, 0xB2, 0x6D, 0x6F, 0x90, 0xA4}; + + /* Check if any bytes differ */ + for (int i = 0; i < 8; i++) { + if (key[i] != first_8_bytes[i]) { + return false; + } + } + + /* The first 8 bytes matched the dummy key, so it is most likely the dummy key */ + return true; +#else + return false; +#endif +} + +void tfm_plat_provisioning_check_for_dummy_keys(void) +{ + if (dummy_key_is_present()) { + SPMLOG_ERRMSG("This device was provisioned with dummy keys and is NOT secure."); + } +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/nrf_provisioning.h b/nrfdemo/build/tfm/api_ns/platform/common/nrf_provisioning.h new file mode 100644 index 0000000..ebba4e4 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/nrf_provisioning.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2022 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +/** + * \brief Update the security lifecycle in OTP + * + * Check if this is valid transition according to the current state and update + * the OTP to transition into the new state. + * + * \param slc Must be the same or the successor state of the current one. + * + * \retval 0 Update was successful. + * \retval -EREADLCS Error on reading the current state + * \retval -EINVALIDLCS Invalid next state + */ +int tfm_attest_update_security_lifecycle_otp(enum tfm_security_lifecycle_t slc); diff --git a/nrfdemo/build/tfm/api_ns/platform/common/ns_fault_service.c b/nrfdemo/build/tfm/api_ns/platform/common/ns_fault_service.c new file mode 100644 index 0000000..d8be284 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/ns_fault_service.c @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include "cmsis.h" +#include "tfm_spm_log.h" +#include "config_tfm.h" +#include "exception_info.h" +#include "nrf_exception_info.h" +#include "tfm_arch.h" +#include "tfm_ioctl_api.h" +#include <tfm_hal_isolation.h> +#include "handle_attr.h" + +/* The goal of this feature is to allow the non-secure to handle the exceptions that are + * triggered by non-secure but the exception is targeting secure. + * + * Banked Exceptions: + * These exceptions have their individual pending bits and will target the security state + * that they are taken from. + * + * These exceptions are banked: + * - HardFault + * - MemManageFault + * - UsageFault + * - SVCall + * - PendSV + * - Systick + * + * These exceptions are not banked: + * - Reset + * - NMI + * - BusFault + * - SecureFault + * - DebugMonitor + * - External Interrupt + * + * AICR.PRIS bit: + * Prioritize Secure interrupts. All secure exceptions take priority over the non-secure + * TF-M enables this + * + * AICR.BFHFNMINS bit: + * Enable BusFault HardFault and NMI to target non-secure. + * Since HardFault is banked this wil target the security state it is taken from, the others + * will always target non-secure. + * The effect of enabling this and PRIS at the same time is UNDEFINED. + * + * External interrupts target security state based on NVIC target state configuration. + * The SPU interrupt has been configured to target secure state in target_cfg.c + * + * The SPU fault handler is just an extension to of the BusFault or SecureFault handler + * that is triggered by events external to the CPU, such as an EasyDMA access. + */ + +#if SPU_IRQn +#define EXCEPTION_TYPE_SPUFAULT (NVIC_USER_IRQ_OFFSET + SPU_IRQn) +#endif + +#if SPU00_IRQn +#define EXCEPTION_TYPE_SPU00FAULT (NVIC_USER_IRQ_OFFSET + SPU00_IRQn) +#endif + +#if SPU10_IRQn +#define EXCEPTION_TYPE_SPU10FAULT (NVIC_USER_IRQ_OFFSET + SPU10_IRQn) +#endif + +#if SPU20_IRQn +#define EXCEPTION_TYPE_SPU20FAULT (NVIC_USER_IRQ_OFFSET + SPU20_IRQn) +#endif + +#if SPU30_IRQn +#define EXCEPTION_TYPE_SPU30FAULT (NVIC_USER_IRQ_OFFSET + SPU30_IRQn) +#endif + +typedef void (*ns_funcptr)(void) __attribute__((cmse_nonsecure_call)); + +static struct tfm_ns_fault_service_handler_context *ns_callback_context; +static ns_funcptr ns_callback; + +int ns_fault_service_set_handler(struct tfm_ns_fault_service_handler_context *context, + tfm_ns_fault_service_handler_callback callback) +{ + ns_callback_context = context; + ns_callback = (ns_funcptr)callback; + + return 0; +} + +void call_ns_callback(struct exception_info_t *exc_info) +{ + struct nrf_exception_info spu_ctx; + + /* When an exception is triggered by the nonsecure the exception frame + * is stacked on the non-secure stack. + * If the non-secure stack is not pointing to valid memory for the + * nonsecure then a nested exception i.e HardFault is triggered. + * Since we don't provide the callback when a HardFault is triggered it + * is impossible that EXC_FRAME_COPY contains secure memory, and it is + * safe to copy this to non-secure. + */ + ns_callback_context->frame.r0 = exc_info->EXC_FRAME_COPY[0]; + ns_callback_context->frame.r1 = exc_info->EXC_FRAME_COPY[1]; + ns_callback_context->frame.r2 = exc_info->EXC_FRAME_COPY[2]; + ns_callback_context->frame.r3 = exc_info->EXC_FRAME_COPY[3]; + ns_callback_context->frame.r12 = exc_info->EXC_FRAME_COPY[4]; + ns_callback_context->frame.lr = exc_info->EXC_FRAME_COPY[5]; + ns_callback_context->frame.pc = exc_info->EXC_FRAME_COPY[6]; + ns_callback_context->frame.xpsr = exc_info->EXC_FRAME_COPY[7]; + + ns_callback_context->registers.r4 = exc_info->CALLEE_SAVED_COPY[0]; + ns_callback_context->registers.r5 = exc_info->CALLEE_SAVED_COPY[1]; + ns_callback_context->registers.r6 = exc_info->CALLEE_SAVED_COPY[2]; + ns_callback_context->registers.r7 = exc_info->CALLEE_SAVED_COPY[3]; + ns_callback_context->registers.r8 = exc_info->CALLEE_SAVED_COPY[4]; + ns_callback_context->registers.r9 = exc_info->CALLEE_SAVED_COPY[5]; + ns_callback_context->registers.r10 = exc_info->CALLEE_SAVED_COPY[6]; + ns_callback_context->registers.r11 = exc_info->CALLEE_SAVED_COPY[7]; + + ns_callback_context->status.cfsr = exc_info->CFSR; + ns_callback_context->status.hfsr = exc_info->HFSR; + ns_callback_context->status.sfsr = exc_info->SFSR; + ns_callback_context->status.bfar = exc_info->BFAR; + ns_callback_context->status.mmfar = exc_info->MMFAR; + ns_callback_context->status.sfar = exc_info->SFAR; + + ns_callback_context->status.msp = __TZ_get_MSP_NS(); + ns_callback_context->status.psp = __TZ_get_PSP_NS(); + ns_callback_context->status.exc_return = exc_info->EXC_RETURN; + ns_callback_context->status.control = __TZ_get_CONTROL_NS(); + ns_callback_context->status.vectactive = exc_info->VECTACTIVE; + + nrf_exception_info_get_context(&spu_ctx); + ns_callback_context->status.spu_events = spu_ctx.events; + + ns_callback_context->valid = true; + + ns_callback(); +} + +void ns_fault_service_call_handler(void) +{ + struct exception_info_t exc_ctx; + + tfm_exception_info_get_context(&exc_ctx); + + const bool exc_ctx_valid = exc_ctx.EXC_RETURN != 0x0; + + if (!exc_ctx_valid || is_return_secure_stack(exc_ctx.EXC_RETURN)) { + /* If exception is triggered by secure continue with secure + * fault handling. + */ + return; + } + + switch (exc_ctx.VECTACTIVE) { + case EXCEPTION_TYPE_SECUREFAULT: + case EXCEPTION_TYPE_BUSFAULT: +#ifdef EXCEPTION_TYPE_SPUFAULT + case EXCEPTION_TYPE_SPUFAULT: +#endif + +#ifdef EXCEPTION_TYPE_SPU00FAULT + case EXCEPTION_TYPE_SPU00FAULT: +#endif + +#ifdef EXCEPTION_TYPE_SPU10FAULT + case EXCEPTION_TYPE_SPU10FAULT: +#endif + +#ifdef EXCEPTION_TYPE_SPU20FAULT + case EXCEPTION_TYPE_SPU20FAULT: +#endif + +#ifdef EXCEPTION_TYPE_SPU30FAULT + case EXCEPTION_TYPE_SPU30FAULT: +#endif + break; + default: + /* Always handle HardFaults in secure. + * UsageFault and MemManageFault are banked and they will be + * triggered in non-secure when fault originates in non-secure. + */ + return; + } + + if (ns_callback) { + call_ns_callback(&exc_ctx); + } + /* If no callback or the callback returns we continue with the + * configured TF-M panic behavior. + */ +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/tfm_hal_platform.c b/nrfdemo/build/tfm/api_ns/platform/common/tfm_hal_platform.c new file mode 100644 index 0000000..ca8919e --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/tfm_hal_platform.c @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2021 - 2022 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include <autoconf.h> + +#if defined(TFM_PARTITION_CRYPTO) && defined(CONFIG_HAS_HW_NRF_CC3XX) +#include <nrf_cc3xx_platform.h> +#include <nrf_cc3xx_platform_ctr_drbg.h> +#endif + +#if defined(NRF_PROVISIONING) +#include "tfm_attest_hal.h" +#endif /* defined(NRF_PROVISIONING) */ + +#include "tfm_hal_platform.h" +#include "tfm_hal_platform_common.h" +#include "cmsis.h" +#include "uart_stdout.h" +#include "tfm_spm_log.h" + +#ifdef CONFIG_HW_UNIQUE_KEY +#include "hw_unique_key.h" +#endif + +#include "config_tfm.h" +#include "exception_info.h" +#include "tfm_arch.h" + +#if defined(TFM_PARTITION_CRYPTO) +static enum tfm_hal_status_t crypto_platform_init(void) +{ + int err = 0; + +#ifdef CONFIG_HAS_HW_NRF_CC3XX + /* Initialize the nrf_cc3xx runtime */ +#if !CRYPTO_RNG_MODULE_ENABLED + err = nrf_cc3xx_platform_init_no_rng(); +#elif defined(CONFIG_PSA_NEED_CC3XX_CTR_DRBG_DRIVER) + err = nrf_cc3xx_platform_init(); +#elif defined(CONFIG_PSA_NEED_CC3XX_HMAC_DRBG_DRIVER) + err = nrf_cc3xx_platform_init_hmac_drbg(); +#else +#error "Please enable either PSA_WANT_ALG_CTR_DRBG or PSA_WANT_ALG_HMAC_DRBG" +#endif + + if (err) { + return TFM_HAL_ERROR_BAD_STATE; + } +#endif /* CONFIG_HAS_HW_NRF_CC3XX */ + +#ifdef CONFIG_HW_UNIQUE_KEY_RANDOM + if (!hw_unique_key_are_any_written()) { + SPMLOG_INFMSG("Writing random Hardware Unique Keys to the KMU.\r\n"); + err = hw_unique_key_write_random(); + if (err != HW_UNIQUE_KEY_SUCCESS) { + SPMLOG_DBGMSGVAL("hw_unique_key_write_random failed with error code:", err); + return TFM_HAL_ERROR_BAD_STATE; + } + SPMLOG_INFMSG("Success\r\n"); + } +#endif /* CONFIG_HW_UNIQUE_KEY_RANDOM */ + (void)err; + return TFM_HAL_SUCCESS; +} +#endif /* defined(TFM_PARTITION_CRYPTO) */ + +/* To write into AIRCR register, 0x5FA value must be written to the VECTKEY field, + * otherwise the processor ignores the write. + */ +#define AIRCR_VECTKEY_PERMIT_WRITE ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)) + +static void allow_nonsecure_reset(void) +{ + uint32_t reg_value = SCB->AIRCR; + + /* Clear SCB_AIRCR_VECTKEY value */ + reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk); + + /* Clear SCB_AIRC_SYSRESETREQS value */ + reg_value &= ~(uint32_t)(SCB_AIRCR_SYSRESETREQS_Msk); + + /* Add VECTKEY value needed to write the register. */ + reg_value |= (uint32_t)(AIRCR_VECTKEY_PERMIT_WRITE); + + SCB->AIRCR = reg_value; +} + +#if CONFIG_NRF_GPIO0_PIN_MASK_SECURE || CONFIG_NRF_GPIO1_PIN_MASK_SECURE +static void maybe_log_for_gpio_port(uint32_t gpio_port, uint32_t secure_pin_mask) +{ + if (secure_pin_mask == 0) { + return; + } + + SPMLOG_INFMSG("Pins have been configured as secure.\r\n"); + SPMLOG_INFMSGVAL("GPIO port: ", gpio_port); + + for (int i = 0; i < 32; i++) { + if (secure_pin_mask & (1 << i)) { + SPMLOG_INFMSGVAL("Pin: ", i); + } + } +} +#endif + +static void log_pin_security_configuration(void) +{ +#if CONFIG_NRF_GPIO0_PIN_MASK_SECURE + maybe_log_for_gpio_port(0, CONFIG_NRF_GPIO0_PIN_MASK_SECURE); +#endif +#if CONFIG_NRF_GPIO1_PIN_MASK_SECURE + maybe_log_for_gpio_port(1, CONFIG_NRF_GPIO1_PIN_MASK_SECURE); +#endif +#if !CONFIG_NRF_GPIO0_PIN_MASK_SECURE && !CONFIG_NRF_GPIO1_PIN_MASK_SECURE + SPMLOG_INFMSG("All pins have been configured as non-secure\r\n"); +#endif +} + +enum tfm_hal_status_t tfm_hal_platform_init(void) +{ + enum tfm_hal_status_t status; + + status = tfm_hal_platform_common_init(); + if (status != TFM_HAL_SUCCESS) { + return status; + } + +#if defined(TFM_PARTITION_CRYPTO) + status = crypto_platform_init(); + if (status != TFM_HAL_SUCCESS) { + return status; + } +#endif /* defined(TFM_PARTITION_CRYPTO) */ + +#if defined(NRF_ALLOW_NON_SECURE_RESET) + allow_nonsecure_reset(); +#endif + +/* When NRF_PROVISIONING is enabled we can either be in the lifecycle state "provisioning" or + * "secured", we don't support any other lifecycle states. This ensures that TF-M will not + * continue booting when an unsupported state is present. + */ +#if defined(NRF_PROVISIONING) + enum tfm_security_lifecycle_t lcs = tfm_attest_hal_get_security_lifecycle(); + + if (lcs != TFM_SLC_PSA_ROT_PROVISIONING && lcs != TFM_SLC_SECURED) { + return TFM_HAL_ERROR_BAD_STATE; + } +#endif /* defined(NRF_PROVISIONING) */ + + log_pin_security_configuration(); + + return TFM_HAL_SUCCESS; +} diff --git a/nrfdemo/build/tfm/api_ns/platform/common/tfm_hal_reset_halt.c b/nrfdemo/build/tfm/api_ns/platform/common/tfm_hal_reset_halt.c new file mode 100644 index 0000000..db9aa95 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/tfm_hal_reset_halt.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include "cmsis.h" +#include "tfm_hal_platform.h" + +#if NRF_ALLOW_NON_SECURE_FAULT_HANDLING +#include "ns_fault_service.h" +#endif /* CONFIG_TFM_ALLOW_NON_SECURE_FAULT_HANDLING */ + +void tfm_hal_system_halt(void) +{ +#if NRF_ALLOW_NON_SECURE_FAULT_HANDLING + ns_fault_service_call_handler(); +#endif + + /* + * Disable IRQs to stop all threads, not just the thread that + * halted the system. + */ + __disable_irq(); + + /* + * Enter sleep to reduce power consumption and do it in a loop in + * case a signal wakes up the CPU. + */ + while (1) { + __WFE(); + } +} + +void tfm_hal_system_reset(void) +{ +#if NRF_ALLOW_NON_SECURE_FAULT_HANDLING + ns_fault_service_call_handler(); +#endif + + NVIC_SystemReset(); +} |