diff options
Diffstat (limited to 'nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition')
| -rw-r--r-- | nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/flash_layout.h | 242 | ||||
| -rw-r--r-- | nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/region_defs.h | 230 |
2 files changed, 472 insertions, 0 deletions
diff --git a/nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/flash_layout.h b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/flash_layout.h new file mode 100644 index 0000000..ca15bda --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/flash_layout.h @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +/* Flash layout on nRF91 with BL2: + * + * 0x0000_0000 BL2 - MCUBoot (64 KB) + * 0x0001_0000 Primary image area (448 KB): + * 0x0001_0000 Secure image primary (256 KB) + * 0x0005_0000 Non-secure image primary (192 KB) + * 0x0008_0000 Secondary image area (448 KB): + * 0x0008_0000 Secure image secondary (256 KB) + * 0x000c_0000 Non-secure image secondary (192 KB) + * 0x000f_0000 Protected Storage Area (16 KB) + * 0x000f_4000 Internal Trusted Storage Area (8 KB) + * 0x000f_6000 OTP / NV counters area (8 KB) + * 0x000f_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + * + * Flash layout on nRF91 without BL2: + * + * 0x0000_0000 Primary image area (960 KB): + * 0x0000_0000 Secure image primary (480 KB) + * 0x0007_8000 Non-secure image primary (480 KB) + * 0x000f_0000 Protected Storage Area (16 KB) + * 0x000f_4000 Internal Trusted Storage Area (8 KB) + * 0x000f_6000 OTP / NV counters area (8 KB) + * 0x000f_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_base_address.h to access flash related defines. To resolve + * this some of the values are redefined here with different names, these are + * marked with comment. + */ + +/* Size of a Secure and of a Non-secure image */ +#ifdef PSA_API_TEST_IPC +/* Firmware Framework test suites */ +#define FLASH_S_PARTITION_SIZE (0x48000) /* S partition: 288 kB*/ +#define FLASH_NS_PARTITION_SIZE (0x28000) /* NS partition: 160 kB*/ +#else +#define FLASH_S_PARTITION_SIZE (0x40000) /* S partition: 256 kB*/ +#define FLASH_NS_PARTITION_SIZE (0x30000) /* NS partition: 192 kB*/ +#endif + +#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) +#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE +#else +#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE +#endif +/* Sector size of the embedded flash hardware (erase/program) */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB. Flash memory program/erase operations have a page granularity. */ + +/* FLASH size */ +#define FLASH_TOTAL_SIZE (0x100000) /* 1024 kB. */ + +/* Flash layout info for BL2 bootloader */ +#define FLASH_BASE_ADDRESS (0x00000000) + + +/* Offset and size definitions of the flash partitions that are handled by the + * bootloader. The image swapping is done between IMAGE_PRIMARY and + * IMAGE_SECONDARY, SCRATCH is used as a temporary storage during image + * swapping. + */ +#define FLASH_AREA_BL2_OFFSET (0x0) +#define FLASH_AREA_BL2_SIZE (0x10000) /* 64 KB */ + +#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1) +/* Secure + Non-secure image primary slot */ +#define FLASH_AREA_0_ID (1) +#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE) +#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) +/* Secure + Non-secure secondary slot */ +#define FLASH_AREA_2_ID (FLASH_AREA_0_ID + 1) +#define FLASH_AREA_2_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) +#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) +/* Not used, only the Non-swapping firmware upgrade operation + * is supported on nRF91. + */ +#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1) +#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) +#define FLASH_AREA_SCRATCH_SIZE (0) +/* Maximum number of image sectors supported by the bootloader. */ +#define MCUBOOT_MAX_IMG_SECTORS ((FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) / \ + FLASH_AREA_IMAGE_SECTOR_SIZE) +#elif (MCUBOOT_IMAGE_NUMBER == 2) +/* Secure image primary slot */ +#define FLASH_AREA_0_ID (1) +#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE) +#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE) +/* Non-secure image primary slot */ +#define FLASH_AREA_1_ID (FLASH_AREA_0_ID + 1) +#define FLASH_AREA_1_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) +#define FLASH_AREA_1_SIZE (FLASH_NS_PARTITION_SIZE) +/* Secure image secondary slot */ +#define FLASH_AREA_2_ID (FLASH_AREA_1_ID + 1) +#define FLASH_AREA_2_OFFSET (FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE) +#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE) +/* Non-secure image secondary slot */ +#define FLASH_AREA_3_ID (FLASH_AREA_2_ID + 1) +#define FLASH_AREA_3_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) +#define FLASH_AREA_3_SIZE (FLASH_NS_PARTITION_SIZE) +/* Not used, only the Non-swapping firmware upgrade operation + * is supported on nRF91. + */ +#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1) +#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE) +#define FLASH_AREA_SCRATCH_SIZE (0) +/* Maximum number of image sectors supported by the bootloader. */ +#define MCUBOOT_MAX_IMG_SECTORS (FLASH_MAX_PARTITION_SIZE / \ + FLASH_AREA_IMAGE_SECTOR_SIZE) +#else /* MCUBOOT_IMAGE_NUMBER > 2 */ +#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!" +#endif /* MCUBOOT_IMAGE_NUMBER */ + +/* Not used, only the Non-swapping firmware upgrade operation + * is supported on nRF91. The maximum number of status entries + * supported by the bootloader. + */ +#define MCUBOOT_STATUS_MAX_ENTRIES (0) + + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (FLASH_AREA_SCRATCH_OFFSET + \ + FLASH_AREA_SCRATCH_SIZE) +#define FLASH_PS_AREA_SIZE (0x4000) /* 16 KB */ + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + \ + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE (0x2000) /* 8 KB */ + +/* OTP_definitions */ +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + \ + FLASH_ITS_AREA_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE * 2) +#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + +/* Non-secure storage region */ +#define NRF_FLASH_NS_STORAGE_AREA_OFFSET (FLASH_TOTAL_SIZE - \ + NRF_FLASH_NS_STORAGE_AREA_SIZE) +#define NRF_FLASH_NS_STORAGE_AREA_SIZE (0x8000) /* 32 KB */ + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_OFFSET (0x0) +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE + +#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + \ + SECURE_IMAGE_MAX_SIZE) +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +/* Flash device name used by BL2 + * Name is defined in flash driver file: Driver_Flash.c + */ +#define FLASH_DEV_NAME Driver_FLASH0 +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x4) + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Size of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x4) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Size of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x4) + +/* OTP / NV counter definitions */ +#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) +#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET +#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE +#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \ + TFM_OTP_NV_COUNTERS_AREA_SIZE) + +/* Use Flash memory to store Code data */ +#define FLASH_BASE_ADDRESS (0x00000000) +#define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS +#define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS + +/* Use SRAM memory to store RW data */ +#define SRAM_BASE_ADDRESS (0x20000000) +#define S_RAM_ALIAS_BASE SRAM_BASE_ADDRESS +#define NS_RAM_ALIAS_BASE SRAM_BASE_ADDRESS + +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE +#define TOTAL_RAM_SIZE (0x00040000) /* 256 kB */ + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/region_defs.h b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/region_defs.h new file mode 100644 index 0000000..4a4ad59 --- /dev/null +++ b/nrfdemo/build/tfm/api_ns/platform/common/nrf91/partition/region_defs.h @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#define BL2_HEAP_SIZE (0x00001000) +#define BL2_MSP_STACK_SIZE (0x00001800) + +#ifdef ENABLE_HEAP + #define S_HEAP_SIZE (0x0000200) +#endif + +#define S_MSP_STACK_SIZE (0x00000800) +#define S_PSP_STACK_SIZE (0x00000800) + +#define NS_HEAP_SIZE (0x00001000) +#define NS_STACK_SIZE (0x000001E0) + +/* Size of nRF SPU (Nordic IDAU) regions */ +#define SPU_FLASH_REGION_SIZE (0x00008000) +#define SPU_SRAM_REGION_SIZE (0x00002000) + +/* + * SPU flash region granularity is 32 KB on nRF91. Alignment + * of partitions is defined in accordance with this constraint. + */ +#ifdef NRF_NS_SECONDARY +#ifndef LINK_TO_SECONDARY_PARTITION +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#endif /* !LINK_TO_SECONDARY_PARTITION */ +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0) +#endif /* NRF_NS_SECONDARY */ + +#ifndef LINK_TO_SECONDARY_PARTITION +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \ + + FLASH_S_PARTITION_SIZE) +#else +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET \ + + FLASH_S_PARTITION_SIZE) +#endif /* !LINK_TO_SECONDARY_PARTITION */ + +/* Boot partition structure if MCUBoot is used: + * 0x0_0000 Bootloader header + * 0x0_0400 Image area + * 0x0_FC00 Trailer + */ +/* IMAGE_CODE_SIZE is the space available for the software binary image. + * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE + * because we reserve space for the image header and trailer introduced + * by the bootloader. + */ + +#if (!defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)) && \ + (NS_IMAGE_PRIMARY_PARTITION_OFFSET > S_IMAGE_PRIMARY_PARTITION_OFFSET) +/* If secure image and nonsecure image are concatenated, and nonsecure image + * locates at the higher memory range, then the secure image does not need + * the trailer area. + */ +#define IMAGE_S_CODE_SIZE \ + (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE) +#else +#define IMAGE_S_CODE_SIZE \ + (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) +#endif + +#define IMAGE_NS_CODE_SIZE \ + (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_IMAGE_PRIMARY_AREA_OFFSET \ + (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) +#define S_CODE_SIZE (IMAGE_S_CODE_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_START (S_RAM_ALIAS(0x0)) +/* Assign to SPE the minimum amount of RAM (aligned to the SPU region boundary) + * that is needed for the most demanding configuration, which turns out to be + * the RegressionIPC one. */ +#define S_DATA_SIZE 0x16000 /* 88 KB */ +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +#define S_CODE_VECTOR_TABLE_SIZE (0x144) + +#if defined(NULL_POINTER_EXCEPTION_DETECTION) && S_CODE_START == 0 +/* If this image is placed at the beginning of flash make sure we + * don't put any code in the first 256 bytes of flash as that area + * is used for null-pointer dereference detection. + */ +#define TFM_LINKER_CODE_START_RESERVED (256) +#if S_CODE_VECTOR_TABLE_SIZE < TFM_LINKER_CODE_START_RESERVED +#error "The interrupt table is too short too for null pointer detection" +#endif +#endif + +/* The veneers needs to be placed at the end of the secure image. + * This is because the NCS sub-region is defined as starting at the highest + * address of an SPU region and going downwards. + */ +#define TFM_LINKER_VENEERS_LOCATION_END +/* The CMSE veneers shall be placed in an NSC region + * which will be placed in a secure SPU region with the given alignment. + */ +#define TFM_LINKER_VENEERS_SIZE (0x400) +/* The Nordic SPU has different alignment requirements than the ARM SAU, so + * these override the default start and end alignments. */ +#define TFM_LINKER_VENEERS_START \ + (ALIGN(SPU_FLASH_REGION_SIZE) - TFM_LINKER_VENEERS_SIZE + \ + (. > (ALIGN(SPU_FLASH_REGION_SIZE) - TFM_LINKER_VENEERS_SIZE) \ + ? SPU_FLASH_REGION_SIZE : 0)) + +#define TFM_LINKER_VENEERS_END ALIGN(SPU_FLASH_REGION_SIZE) + +/* Non-secure regions */ +#define NS_IMAGE_PRIMARY_AREA_OFFSET \ + (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) +#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) +#ifdef PSA_API_TEST_IPC +/* Last SRAM region must be kept secure for PSA FF tests */ +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - SPU_SRAM_REGION_SIZE) +#else +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#endif +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for SPU configuration */ +#define NS_PARTITION_START \ + (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)) +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Secondary partition for new images in case of firmware upgrade */ +#define SECONDARY_PARTITION_START \ + (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET)) +#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) + +/* Non-secure storage region */ +#ifdef NRF_NS_STORAGE +#define NRF_NS_STORAGE_PARTITION_START \ + (NS_ROM_ALIAS(NRF_FLASH_NS_STORAGE_AREA_OFFSET)) +#define NRF_NS_STORAGE_PARTITION_SIZE (NRF_FLASH_NS_STORAGE_AREA_SIZE) +#endif /* NRF_NS_STORAGE */ + +#ifdef BL2 +/* Bootloader regions */ +#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET)) +#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE) +#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) + +#define BL2_DATA_START (S_RAM_ALIAS(0x0)) +#define BL2_DATA_SIZE (TOTAL_RAM_SIZE) +#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) +#endif /* BL2 */ + +/* Shared data area between bootloader and runtime firmware. + * Shared data area is allocated at the beginning of the RAM, it is overlapping + * with TF-M Secure code's MSP stack + */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE +#define BOOT_TFM_SHARED_DATA_SIZE (0x400) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ + BOOT_TFM_SHARED_DATA_SIZE - 1) + +/* Regions used by psa-arch-tests to keep state */ +#define PSA_TEST_SCRATCH_AREA_SIZE (0x400) + +#ifdef PSA_API_TEST_IPC +/* Firmware Framework test suites */ +#define FF_TEST_PARTITION_SIZE 0x100 +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE - \ + FF_TEST_PARTITION_SIZE) + +/* The psa-arch-tests implementation requires that the test partitions are + * placed in this specific order: + * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER + * + * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER + * must be in SPE. + * + * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation, + * and it should be placed at the end of the NSPE area, after + * PSA_TEST_SCRATCH_AREA. + */ +#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1) +#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#else +/* Development APIs test suites */ +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE) +#endif /* PSA_API_TEST_IPC */ + +#endif /* __REGION_DEFS_H__ */ |